This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377D: SCI Receiver over Run Error

Part Number: TMS320F28377D


Tool/software:

Hello Team,

I am using RS485 with TMS320F28377D controller and three controller are connected on same RS485 Bus.

I am using four wire RS485 Transceiver on all three board.

After Multiple event some time any of board receiver ISR is stop to trigger. After debug i came to know RXERROR bit of SCIRXST receive status register is High

and it shows SCI over Run flag.

I have tried to reset with SCIRST Register but it is not come to healthy state again.

Please suggest way to remove this error from SCI module or way to reset it when it comes.

Regards,

Bharat

  • Hi Bharant,

    Oddly driver lib clear RX OVF register bit does not work nor clear the RX INT flag. Perhaps add below code patch with MCU class peripheral offset register addresses into the RX ISR routine before RX FIFO input calls, it actually works on x39c, x49c. That RX OVF flag drove crazy finally had enough wrote below code snip work around. You may lose the FIFO data though can resend on NAK sent to the client originated data.

      

        /* Check SCIFFRX register FIFO has overflowed */
        //if(SCI_getOverflowStatus(SCIB_BASE))
        if((HWREGH(SCIB_BASE + SCI_O_FFRX) & SCI_FFRX_RXFFOVF) == SCI_FFRX_RXFFOVF)
        {
            // Acknowledge interrupt from PIE group 9
            Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP9);
            /* Clear Rx overflow status */
            //SCI_clearOverflowStatus(SCIB_BASE);
    
            /* Check SCIFFRX register FIFO has overflowed */
            if(HWREGH(SCIB_BASE + SCI_O_FFRX) == 0xB0A6)//0xAEA6
            {
                /* Clear the RXFIFO OVF flag bit */
                HWREGH(SCIB_BASE + SCI_O_FFRX) |=  0x68A6;
                /* Allow RXFIFO flag bit to reset 2ms */
                DEVICE_DELAY_US(2000);
                /* Clear RXFIFO RXINT flag bit */
                HWREGH(SCIB_BASE + SCI_O_FFRX) |= 0x2066;
            }
    
            /* SCIA Prints event message */
            SCIprintf("\n*ClRxOVF&RxIntRXD\n");
        }

  • Hi Bharat,

    A few questions:

    • Are you actively trying to send/receive data while doing a channel reset?
    • Can you please try using the SW RESET as well?
    • Where are you calling the reset? And which other error flags are being set (RXERROR is a logical OR of the break detect, framing error, overrun, and parity error enable flags)?

    Best Regards,

    Allison