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TMS320F280039: About the phase shift and synchronization issues of EPWM

Lawrence Wang
Intellectual 1210 points
Part Number: TMS320F280039


Tool/software:

Hi experts,

Please refer to the attached images. Channel 1 corresponds to PWM1A, Channel 2 to PWM1B, Channel 3 to PWM2A, and Channel 4 to PWM2B.

  • Synchronization Issue Between PWM1 and PWM2:
    As shown in Image 1, there is no synchronization error between Channel 1 and Channel 3. However, during previous tests, a synchronization error of approximately 16ns was observed, which could not be eliminated. This behavior differs from the current observation.


    According to documentation, synchronization errors are expected.
    The question is whether this synchronization error is persistent and cannot be eliminated, or if it is uncertain—sometimes present, sometimes absent, and uncontrollable.

  • Phase Shift Issue Between PWM1 and PWM2:
    As shown in the configuration code above, phase shift has been configured. However, the first PWM cycle of Channel 1 and Channel 3 does not reflect the phase shift. The configured phase shift only appears starting from the second PWM cycle.
    Please refer to Images 2 and 3 for details.


    Is this behavior normal, or is there an issue with the configuration?

Code Configuration (Partial):

    /*-------ePWM1A/B-----------------*/

    //configure counter mode

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;

    EPwm1Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;

    EPwm1Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;

 

//    EPwm1Regs.TBCTL.bit.SWFSYNC = 0u;

    EPwm1Regs.EPWMSYNCOUTEN.bit.ZEROEN = 1;

//    EPwm1Regs.EPWMSYNCOUTEN.bit.SWEN = 0;

 

    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;            // set SHADOW load

    //Period = 120M /Freq_PWM. Period100k = 120M/100K=1200， TBPRD = Period/2 +1 = 601;

    EPwm1Regs.TBPRD = PWM_PERIOD_100K;//PSFB_PEROID_NORMAL-1;

    EPwm1Regs.TBPHS.bit.TBPHS = 0u;

    EPwm1Regs.TBCTR = 0u;

    EPwm1Regs.CMPA.bit.CMPA = PWM_PERIOD_100K>>1;//(PSFB_PEROID_NORMAL-1)>>1;              // Fix duty at 50%

//    EPwm1Regs.CMPB.bit.CMPB = EPwm1Regs.CMPA.bit.CMPA;//EPwm1Regs.CMPA.bit.CMPA - 10

    //configure the shadow register, load CMP when CTR == 0

    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

//    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

//    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    //configure action qualifier register

    EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;              //output high level when TBCTR=0

    EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;            //output low level when TBTCR=CMPA

 

    //configure dead band register

    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;

    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

    EPwm1Regs.DBRED.bit.DBRED = 0u;         //rising edge time delay

    EPwm1Regs.DBFED.bit.DBFED = 0u;         //falling edge time delay

 

    /*-------ePWM2A/B-----------------*/

    //configure counter mode

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;

    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;

    EPwm2Regs.TBCTL.bit.HSPCLKDIV = EPWM_HSCLOCK_DIVIDER_1;

    EPwm2Regs.TBCTL.bit.CLKDIV = EPWM_CLOCK_DIVIDER_1;

 

    EPwm2Regs.TBCTL.bit.PHSDIR = 0;

 

//    EPwm2Regs.TBCTL.bit.SWFSYNC = 0u;

    EPwm2Regs.EPWMSYNCOUTEN.bit.ZEROEN = 1;

    EPwm2Regs.EPWMSYNCINSEL.bit.SEL = 1;

 

    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;            // set SHADOW load

    //Period = 120M /Freq_PWM. Period100k = 120M/100K=1200， TBPRD = Period/2 +1 = 601;

    EPwm2Regs.TBPRD = PWM_PERIOD_100K;//PSFB_PEROID_NORMAL-1;

    EPwm2Regs.TBPHS.bit.TBPHS = 100;

    EPwm2Regs.TBCTR = 0;

 

EPwm2Regs.CMPA.bit.CMPA = 300u;

  • 0
    TI__Expert 4690 points

    Hello,

    Make sure not to set TBPHS shift load to zero, but at least to 2 to take into account the delay synchronization,

  • 0 in reply to Stevan Duraskovic
    TI__Intellectual 1210 points

    There are two issues here: the first one is related to PWM phase shifting, and the second one concerns synchronization between PWMs. Could you please provide a response to the first issue?

    Regarding the synchronization issue between PWMs, PWM2 is already delayed by approximately 2 system clock cycles compared to PWM1. When configuring the two TBPHS values, should they be configured on PWM1 or PWM2?

    Customer have tested this and found that configuring TBPHS on PWM1 does not improve the delay between PWM2 and PWM1. If configured on PWM2, will the delay worsen?

  • 0 in reply to Lawrence Wang
    TI__Expert 4690 points

    Hello,

    One of your PMWs will be master and the second is in slave mode. PWM1 (master) sends the syncout pulse, the PWM2 (slave) enables phase shift load, and this phase shift load should be at least 2. You should not enable phase shift load on both PWMs, but just on slave PWMs. Hope this helps.

  • 0 in reply to Stevan Duraskovic
    TI__Intellectual 1210 points

    Hi Stevan,

    Our customer has the following inquiry regarding the use of PWM synchronization. Could you please help confirm whether the described PWM synchronization method is reliable and safe under long-term operation and various conditions (e.g., in-vehicle charging scenarios, high CPU load, and other harsh environments)?

    The datasheet mentions that synchronized PWM signals will have a delay of 2 system clock cycles relative to the synchronization source signal. Our testing confirms this behavior: when PWM1 is used as the synchronization source, and its output serves as the synchronization source for PWM2, PWM3, and PWM4, the test results show that PWM2, PWM3, and PWM4 are synchronized, all delayed by 2 system clock cycles relative to PWM1.

    To achieve synchronization among PWM1, PWM2, PWM3, and PWM4, we attempted to use PWM6 as the synchronization source (PWM6 does not output waveforms and is used solely as the synchronization source). The output of PWM6 was used as the synchronization source for PWM1, PWM2, PWM3, and PWM4. The test results show that PWM1, PWM2, PWM3, and PWM4 are synchronized.

    While this approach appears to achieve synchronization among PWM1, PWM2, PWM3, and PWM4, we would like to confirm whether this method is reliable and safe. Specifically, is it safe to use PWM6, which is a later PWM module and does not output waveforms, as the synchronization source?

  • 0 in reply to Lawrence Wang
    TI__Expert 4690 points

    Hello Lawrence,

    The two clock cycle delay will always be there. It is reliable to use PWM1 as a master source and synchronize others to PWM1. You can pick any PWM as a master source.