TMS320F28388D: Event which triggers EMAC_INT_RX

Is there any update regarding this?

Regards,
Ganesh

Hi, 

Can I know the exact macro that you are using?

If it is INT_EMAC_RX0 (for DMA channel0) or INT_EMAC_RX1 (for DMA channel1) , the interrupt gets hit on receive completion event alone.

Hi Gouri Siva,

Thank you for your response.

My use case is to trigger a UDP Send when I receive a UDP packet. We are using the stack provided by TI.  I want to know about both INT_EMAC_RX0 or INT_EMAC_RX1.

When you mention receive completion event, what do you mean by it? The completion of DMA receive, or the completion of the UDP packet being received and processed?

There were some other observations and queries I have:
1) In the case of INT_EMAC_RX0:
i) The ISR given in ethernet.c seems to be used as part of the Receive workflow. f2838xif_transmit in f2838xif.c seems to be enabling the INT_EMAC_RX0 and INT_EMAC_TX0.

ii) On changing the ISR to something we have written, the receive process seems broken.

iii) On the basis of i), Can this interrupt be used for other purposes?

2) In the case of INT_EMAC_RX1:
i) NVIC.NVIC_ISPR0.SETPEND17, NVIC.NVIC_ICPR0.CLRPEND17 and NVIC.NVIC_IABR0.ACTIVE17 are never set. On manually enabling the bits, it enters the ISR without any packets being received at all. What is the event which causes the bits to get set?

Regards,
Ganesh

Hi, 

Thank you for your explanation.

The event which triggers INT_EMAC_RX0 is the DMA receive completion event. At the time of DMA receive completion event, RI bit (6th bit)  of DMA Channel0 Interrupt status register gets set. This will create a peripheral interrupt and reaches NVIC, which will trigger ISR. 

So, if you consider rewriting the ISR, make sure that you clear the RI bit on DMA status register. Also, the packet handling is happening inside the ISR as of now, so make sure that it is not getting disturbed as you make changes in ISR.

Also, if you could share the changes you made on ISR, I can point out the reason for stoppage of receive process.

NVIC channels peripheral interrupts, so the actual source here is the interrupt from Ethernet module (specifically the RI bit of DMA status register).

Hi,

I have attached a zip file containing the generated code and the Simulink model for INT_EMAC_RX0. Similar code can be generated for INT_EMAC_RX1 by changing the selection in the drop down of Hardware Interrupt block. Please let me know if you have any suggestions. Based on your previous response, my understanding is that if we are trying to use INT_EMAC_RX1, we will have to redo all the ethernet initializations with INT_EMAC_RX1 as by default the INT_EMAC_RX0 and INT_EMAC_TX0 interrupts are used. Is my understanding correct?

Regards,
Ganesh

MWModel.zip

Hi, 

Sorry that I am not able to see the block diagram.

I have checked the function EMAC_RX_INT0_Handler from the generated code. I am assuming you are using this function as the receive ISR.

As I mentioned early, receive ISR should clear RI bit of DMA status register, not the NVIC one (In the generated code this case is observed). And mainly you should be taking care of packet handling which is happening inside the receive ISR.

Can I know if you are calling Ethernet_init and lwipinit functions?

So basically, INT_EMAC_RX0 interrupt is triggered when DMA completes data transmission to Rx Buffer location. At ISR level you need to take out the packet and pass to the lwip stack (light weight tcp/ip stack). This is done by a callback function called from ISR to the f2838xif layer. lwip stack will call your udp callback function from where you can process the udp packet.

Can you verify these steps are happening in your code?

Can you verify the steps you followed to write ISR doesn't disturb the normal routine done by already defined receive ISR?

You can compare with the enet_lwip_udp example from C2000ware.

Hi,

Thank you for your prompt response.

I will look into the suggestions given by you. Regarding INT_EMAC_RX1, as I had mentioned in my previous post, would we have to redo all the ethernet initializations? Is there any way of triggering INT_EMAC_RX1 with the default ethernet settings which use INT_EMAC_RX0?

Regards,
Ganesh

Hi, 

You can refer to Ethernet_init function. It initializes both DMA channels. 

Hi,

Thank you for your detailed response regarding the sequence.

In the enet_lwip_udp example, although INT_EMAC_RX1 is passed to Ethernet_initInterface, there seems to be no application of it. The handler is also not registered. Most of the initializations are done internally. This leads to a few queries:

1. What is the use case for this interrupt if it is similar to INT_EMAC_RX0, which receives the packet via DMA and passes it on to the application? Is there some other action it can undertake?
2. Is it possible to use INT_EMAC_RX0 to pass received packet to application1, and INT_EMAC_RX1 to another application/ISR?

Regards,

Ganesh

It is possible to create two different custom ISR to handle INT_EMAC_RX1 and INT_EMAC_RX0. Inside those ISR , you can call Ethernet_removePacketsFromRxQueue API. Only make sure that you pass the exact channel descriptor pointer as parameter to this API, ie, channel 0 for INT_EMAC_RX0 and channel 1 for INT_EMAC_RX1. Also make sure to clear the DMA channel status register.(You can refer the Ethernet_receiveISR implementation in ethernet.c file).