Part Number: TMS320F28P650DH
Tool/software:
Hello, expert. Currently, I am using the SPI_DMA master to write 400 bytes to the DSP slave (PC) every 600us. The first data packet received by the PC is misaligned, while the rest are correct. The SPI is in Mode 3. I have captured the MOSI (yellow) and CLK (blue) signals with an oscilloscope, as shown in Figure 1
The first byte sent by this host is 0xAAAA. From the analysis of the figure, it is not MODE3; MOSI is updated on the falling edge of CLK and sampled on the rising edge of CLK.
-----The normal host sends 0xAAAA, MODE3. The oscilloscope should not capture the waveform in this way. Could you please tell me the reason?-----It was the host that sent the data with a single clock error.
In the normal SPI (host) Mode 3 mode, the waveform CLK should be sent in this way and MOSI should correspond accordingly. However, when the oscilloscope captures CLK and MOSI, it is not like this.
The SPI configuration is as follows: Before the SPI host data, the SPI_FIFO will be disabled, and then the SPI_FIFO will be enabled.
