TMS320F28375D: Program not working

Amtech

Part Number: TMS320F28375D

Tool/software:

Dear Sir,

We have developed control card based on TMS320F28375D controller for our application since 2018. For future enhancement we adds functionality time to time.

One of the functionality i.e Modbus TCP IP based on ethernet runs on CPU2 CLA is working fine.

Now, if we add some piece of code which is not related to Modbus TCP-IP then Modbus TCP-IP functionality is not working properly. If we remove any another code which is not related to it, codes start working.

We are using code composer studio version 8.0 and compiler version TI 18.1.1.LTS. We also checked same code with code composer studio version 12.0 and compiler version TI 22.6.1 LTS but not working properly.

We have doubt on memory mapping. For your reference, we have attached working and non working map file of both CPUs.

Cpu1_map_Not Working.txt Cpu1_map_Working.txt Cpu2_map_Not Working.txt Cpu2_map_Working.txt

5 months ago

0 Delaney Woodward 5 months ago

TI__Mastermind 20990 points

Hello,

I would indeed suspect something memory related if changing different unrelated portions of code are causing the behavior. A few clarifying questions:

Amtech said:
Now, if we add some piece of code

Which part of memory are you modifying here that is causing the issue?

Could you also share your linker cmd file so I can see how each portion of memory is getting allocated?

Are you able to attach a debugger to your MCU so we can see where exactly in the Modbus TCP-IP functionality is changing/getting corrupted?

Best Regards,

Delaney

0 Amtech 5 months ago in reply to Delaney Woodward

Genius 4585 points

Thanks for your prompt reply.

1) Flash E part of memory of CPU2 is modified when problem is occur as per .map file

2) Here, i attached flash_link_cpu1&2 cmd file and Headers_nonbios_cpu1&2 file of non working code.

Fullscreen F2837x_FLASH_lnk_cpu1.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x002800
  /* RAMLS1          	: origin = 0x008800, length = 0x000800*/
   /*RAMLS2      		: origin = 0x009000, length = 0x000800*/
   //RAMLS3      		: origin = 0x009800, length = 0x000800
   //RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000
   RAMGS15          : origin = 0x01B000, length = 0x001000
   RESET           	: origin = 0x3FFFC0, length = 0x000002
   
   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x030000	/* on-chip Flash */
  /* FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
  /* FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
  /* FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
  /* FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
  /* FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   RAMGS12     : origin = 0x018000, length = 0x001000
   RAMGS13     : origin = 0x019000, length = 0x001000

   
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
}


SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHE,      PAGE = 0
   .pinit              : > FLASHE,     PAGE = 0
   .text               : > FLASHE,     PAGE = 0
   codestart           : > BEGIN,       PAGE = 0
   ramfuncs            : LOAD = FLASHE,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0
						 
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
   .ebss               : > RAMLS5       PAGE = 1
   .esysmem            : > RAMLS5       PAGE = 1

   /* Initalized sections go in Flash */
   .econst             : > FLASHA | FLASHB      PAGE = 0
   .switch             : > FLASHA | FLASHB      PAGE = 0


   .reset              : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */

   Filter_RegsFile     : > RAMGS0,	   PAGE = 1
   
   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   
   /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU1TOCPU2RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }  
    
       /* Allocate IQ math areas: */ //37.00
   IQmath			: > FLASHB, PAGE = 0, ALIGN(4)            /* Math Code */
   IQmathTables		: > FLASHC, PAGE = 0, ALIGN(4)

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen F2837xD_FLASH_lnk_cpu2.txt Download

// The user must define CLA_C in the project linker settings if using the
// CLA C compiler
// Project Properties -> C2000 Linker -> Advanced Options -> Command File
// Preprocessing -> --define
--define=CLA_C=1
--define=CLA_MATH_TABLES_IN_ROM=1

#ifdef CLA_C	//37.01.00.7.12
// Define a size for the CLA scratchpad area that will be used
// by the CLA compiler for local symbols and temps
// Also force references to the special symbols that mark the
// scratchpad are.
CLA_SCRATCHPAD_SIZE = 0x400;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start
#endif //CLA_C

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000080, length = 0x000380
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x002800	//37.01.00.7.12


   RAMLS0          	: origin = 0x008000, length = 0x002000 //Ethernet
   /*RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800*/
   RAMLS4      		: origin = 0x00A000, length = 0x001000 //Ethernet
   /*RAMLS5          : origin = 0x00A800, length = 0x000800*/


   RAMGS14          : origin = 0x01A000, length = 0x001000
   RAMGS15          : origin = 0x01B000, length = 0x001000
   RESET       		: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x030000	/* on-chip Flash */
//   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
//   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
//   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
//   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
//   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x00007E     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800


   //RAMLS5          : origin = 0x00A800, length = 0x000800	//37.01.00.7.12
                   
   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   RAMGS11     : origin = 0x017000, length = 0x001000
   RAMGS12     : origin = 0x018000, length = 0x001000
   RAMGS13     : origin = 0x019000, length = 0x001000

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400
   
}


SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHE      PAGE = 0, ALIGN(4)
   .pinit              : > FLASHE,     PAGE = 0, ALIGN(4)
   .text               : > FLASHE      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   ramfuncs            : LOAD = FLASHE,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
						 
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1
   //.ebss               : > RAMLS5       PAGE = 1
   //.esysmem            : > RAMLS5       PAGE = 1
   .ebss               : > RAMLS0       PAGE = 0	//37.01.00.7.12
   .esysmem            : > RAMLS0       PAGE = 0

   /* Initalized sections go in Flash */
   .econst             : > FLASHA | FLASHB      PAGE = 0, ALIGN(4)
   .switch             : > FLASHA | FLASHB      PAGE = 0, ALIGN(4)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */


   /* CLA specific sections */ //Ethernet	//37.01.00.7.12
#if !(CLA_MATH_TABLES_IN_ROM)
   CLA1mathTables   : > RAMLS0,                 PAGE = 0

   //Load tables to Flash and copy over to RAM -- CLA Math Tables in ROM
   CLA1mathTables   :  LOAD = FLASHE,
                       RUN = RAMLS0,
                       RUN_START(_CLA1mathTablesRunStart),
                       LOAD_START(_CLA1mathTablesLoadStart),
                       LOAD_SIZE(_CLA1mathTablesLoadSize),
                       PAGE = 0
#endif //CLA_MATH_TABLES_IN_ROM

   Cla1Prog         : LOAD = FLASHD,
                      RUN = RAMLS4,
                      LOAD_START(_Cla1funcsLoadStart),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      LOAD_SIZE(_Cla1funcsLoadSize),
                      PAGE = 0, ALIGN(4)

   #ifdef CLA_C
   /* CLA C compiler sections */
   // Must be allocated to memory the CLA has write access to
   CLAscratch       :
                     { *.obj(CLAscratch)
                     . += CLA_SCRATCHPAD_SIZE;
                     *.obj(CLAscratch_end) } >  RAMLS0,  PAGE=0

   .scratchpad      : > RAMLS0,       PAGE=0
   .bss_cla		    : > RAMLS0,       PAGE=0
   .const_cla	    :  LOAD = FLASHE,
                       RUN = RAMLS0,
                       RUN_START(_Cla1ConstRunStart),
                       LOAD_START(_Cla1ConstLoadStart),
                       LOAD_SIZE(_Cla1ConstLoadSize),
                       PAGE = 0, ALIGN(4)
	#endif //CLA_C
  
   SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1  
   
   /* The following section definitions are required when using the IPC API Drivers */ 
    GROUP : > CPU2TOCPU1RAM, PAGE = 1 
    {
        PUTBUFFER 
        PUTWRITEIDX 
        GETREADIDX 
    }
    
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }  

       /* Allocate IQ math areas: */ //37.00
   IQmath			: > FLASHB, PAGE = 0, ALIGN(4)            /* Math Code */
   IQmathTables		: > FLASHC, PAGE = 0, ALIGN(4)
    
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen 6765.F2837x_Headers_nonBIOS_cpu1.txt Download

MEMORY
{
 PAGE 0:    /* Program Memory */

 PAGE 1:    /* Data Memory */

   ADCA_RESULT   : origin = 0x000B00, length = 0x000020
   ADCB_RESULT   : origin = 0x000B20, length = 0x000020
   ADCC_RESULT   : origin = 0x000B40, length = 0x000020
   ADCD_RESULT   : origin = 0x000B60, length = 0x000020

   ADCA          : origin = 0x007400, length = 0x000080
   ADCB          : origin = 0x007480, length = 0x000080
   ADCC          : origin = 0x007500, length = 0x000080
   ADCD          : origin = 0x007580, length = 0x000080

   ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080
   
   CLA1          : origin = 0x001400, length = 0x000040     /* CLA registers */

   CLB_XBAR      : origin = 0x007A40, length = 0x000040

   CMPSS1        : origin = 0x005C80, length = 0x000020
   CMPSS2        : origin = 0x005CA0, length = 0x000020
   CMPSS3        : origin = 0x005CC0, length = 0x000020
   CMPSS4        : origin = 0x005CE0, length = 0x000020
   CMPSS5        : origin = 0x005D00, length = 0x000020
   CMPSS6        : origin = 0x005D20, length = 0x000020
   CMPSS7        : origin = 0x005D40, length = 0x000020
   CMPSS8        : origin = 0x005D60, length = 0x000020

   CPU_TIMER0    : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
   CPU_TIMER1    : origin = 0x000C08, length = 0x000008     /* CPU Timer1 registers */
   CPU_TIMER2    : origin = 0x000C10, length = 0x000008     /* CPU Timer2 registers */

   DACA          : origin = 0x005C00, length = 0x000010
   DACB          : origin = 0x005C10, length = 0x000010
   DACC          : origin = 0x005C20, length = 0x000010

   DCANA         : origin = 0x048000, length = 0x001000		/* DCAN A Registers */
   DCANB         : origin = 0x04A000, length = 0x001000		/* DCAN B Registers */

   DMA          : origin = 0x001000, length = 0x000200
   DMACLASRCSEL : origin = 0x007980, length = 0x000040

   ECAP1        : origin = 0x005000, length = 0x000020     /* Enhanced Capture 1 registers */
   ECAP2        : origin = 0x005020, length = 0x000020     /* Enhanced Capture 2 registers */
   ECAP3        : origin = 0x005040, length = 0x000020     /* Enhanced Capture 3 registers */
   ECAP4        : origin = 0x005060, length = 0x000020     /* Enhanced Capture 4 registers */
   ECAP5        : origin = 0x005080, length = 0x000020     /* Enhanced Capture 5 registers */
   ECAP6        : origin = 0x0050A0, length = 0x000020     /* Enhanced Capture 6 registers */
   
   EMIF1        : origin = 0x047000, length = 0x000800
   EMIF2        : origin = 0x047800, length = 0x000800

   EQEP1        : origin = 0x005100, length = 0x000040     /* Enhanced QEP 1 registers */
   EQEP2        : origin = 0x005140, length = 0x000040     /* Enhanced QEP 2 registers */
   EQEP3        : origin = 0x005180, length = 0x000040     /* Enhanced QEP 3 registers */

   EPWM1        : origin = 0x004000, length = 0x000100     /* Enhanced PWM 1 registers */
   EPWM2        : origin = 0x004100, length = 0x000100     /* Enhanced PWM 2 registers */
   EPWM3        : origin = 0x004200, length = 0x000100     /* Enhanced PWM 3 registers */
   EPWM4        : origin = 0x004300, length = 0x000100     /* Enhanced PWM 4 registers */
   EPWM5        : origin = 0x004400, length = 0x000100     /* Enhanced PWM 5 registers */
   EPWM6        : origin = 0x004500, length = 0x000100     /* Enhanced PWM 6 registers */
   EPWM7        : origin = 0x004600, length = 0x000100     /* Enhanced PWM 7 registers */
   EPWM8        : origin = 0x004700, length = 0x000100     /* Enhanced PWM 8 registers */
   EPWM9        : origin = 0x004800, length = 0x000100     /* Enhanced PWM 9 registers */
   EPWM10       : origin = 0x004900, length = 0x000100     /* Enhanced PWM 10 registers */
   EPWM11       : origin = 0x004A00, length = 0x000100     /* Enhanced PWM 11 registers */
   EPWM12       : origin = 0x004B00, length = 0x000100     /* Enhanced PWM 12 registers */

   EPWM_XBAR  	: origin = 0x007A00, length = 0x000040

   FLASH_CTRL  : origin = 0x05F800, length = 0x000300
   FLASH_ECC   : origin = 0x05FB00, length = 0x000040

   GPIOCTRL     : origin = 0x007C00, length = 0x000180     /* GPIO control registers */
   GPIODAT      : origin = 0x007F00, length = 0x000030     /* GPIO data registers */

   GPIO_OUT_XBAR : origin = 0x007A80, length = 0x000040
   HWBIST       : origin = 0x05E000, length = 0x000100     /* HWBIST registers */
   I2CA         : origin = 0x007300, length = 0x000040     /* I2C-A registers */
   I2CB         : origin = 0x007340, length = 0x000040     /* I2C-B registers */

   IPC          : origin = 0x050000, length = 0x001000

   ROMPREFETCH  : origin = 0x05E608, length = 0x000002

   MEMCFG       : origin = 0x05F400, length = 0x000080     /* Mem Config registers */
   EMIF1CONFIG  : origin = 0x05F480, length = 0x000020     /* Emif-1 Config registers */
   EMIF2CONFIG  : origin = 0x05F4A0, length = 0x000020     /* Emif-2 Config registers */
   ACCESSPROTECTION  : origin = 0x05F4C0, length = 0x000040     /* Access Protection registers */
   MEMORYERROR  : origin = 0x05F500, length = 0x000040     /* Access Protection registers */
   ROMWAITSTATE : origin = 0x05F540, length = 0x000002     /* ROM Config registers */
   

   MCBSPA       : origin = 0x006000, length = 0x000040     /* McBSP-A registers */
   MCBSPB       : origin = 0x006040, length = 0x000040     /* McBSP-A registers */

   NMIINTRUPT   : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */

   PIE_CTRL     : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
   PIE_VECT     : origin = 0x000D00, length = 0x000200     /* PIE Vector Table */
   PBIST        : origin = 0x05E200, length = 0x000200     /* PBIST registers */
   SCIA         : origin = 0x007200, length = 0x000010     /* SCI-A registers */
   SCIB         : origin = 0x007210, length = 0x000010     /* SCI-B registers */
   SCIC         : origin = 0x007220, length = 0x000010     /* SCI-C registers */
   SCID         : origin = 0x007230, length = 0x000010     /* SCI-D registers */
   
   SDFM1		: origin = 0x005E00, length = 0x000080	   /* Sigma delta 1 registers */
   SDFM2		: origin = 0x005E80, length = 0x000080	   /* Sigma delta 2 registers */

   SPIA         : origin = 0x006100, length = 0x000010
   SPIB         : origin = 0x006110, length = 0x000010
   SPIC         : origin = 0x006120, length = 0x000010
   SPID         : origin = 0x006130, length = 0x000010

   UPP          : origin = 0x006200, length = 0x000100     /* uPP registers */

   DEV_CFG     : origin = 0x05D000, length = 0x000180
   CLK_CFG     : origin = 0x05D200, length = 0x000100
   CPU_SYS     : origin = 0x05D300, length = 0x000100

   INPUT_XBAR   : origin = 0x007900, length = 0x000020
   XBAR         : origin = 0x007920, length = 0x000020
   TRIG         : origin = 0x007940, length = 0x000010
   WD           : origin = 0x007000, length = 0x000040

   XINT         : origin = 0x007070, length = 0x000010

   DCSM_Z1      : origin = 0x05F000, length = 0x000030     /* Zone 1 Dual code security module registers */
   DCSM_Z2      : origin = 0x05F040, length = 0x000030     /* Zone 2 Dual code security module registers */
   DCSM_COMMON  : origin = 0x05F070, length = 0x000010     /* Common Dual code security module registers */

   DCSM_OTP_Z1  : origin = 0x078800, length = 0x000020     /* Part of Z1 OTP.  LinkPointer/JTAG lock/ Boot Mode */
   DCSM_OTP_Z2  : origin = 0x078900, length = 0x000020     /* Part of Z2 OTP.  LinkPointer/JTAG lock */
}


SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
  UNION run = PIE_VECT, PAGE = 1
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

   AdcaResultFile        : > ADCA_RESULT,  PAGE = 1
   AdcbResultFile        : > ADCB_RESULT,  PAGE = 1
   AdccResultFile        : > ADCC_RESULT,  PAGE = 1
   AdcdResultFile        : > ADCD_RESULT,  PAGE = 1

   AdcaRegsFile          : > ADCA,         PAGE = 1
   AdcbRegsFile          : > ADCB,         PAGE = 1
   AdccRegsFile          : > ADCC,         PAGE = 1
   AdcdRegsFile          : > ADCD,         PAGE = 1

   AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1
   
   Cla1RegsFile          : > CLA1,         PAGE = 1
   Cla1SoftIntRegsFile   : > PIE_CTRL, 	   PAGE = 1, type=DSECT

   ClbXbarRegsFile      : > CLB_XBAR     PAGE = 1

   Cmpss1RegsFile        : > CMPSS1,      PAGE = 1
   Cmpss2RegsFile        : > CMPSS2,      PAGE = 1
   Cmpss3RegsFile        : > CMPSS3,      PAGE = 1
   Cmpss4RegsFile        : > CMPSS4,      PAGE = 1
   Cmpss5RegsFile        : > CMPSS5,      PAGE = 1
   Cmpss6RegsFile        : > CMPSS6,      PAGE = 1
   Cmpss7RegsFile        : > CMPSS7,      PAGE = 1
   Cmpss8RegsFile        : > CMPSS8,      PAGE = 1

   CpuTimer0RegsFile     : > CPU_TIMER0,    PAGE = 1
   CpuTimer1RegsFile     : > CPU_TIMER1,    PAGE = 1
   CpuTimer2RegsFile     : > CPU_TIMER2,    PAGE = 1

   DacaRegsFile          : > DACA          PAGE = 1
   DacbRegsFile          : > DACB          PAGE = 1
   DaccRegsFile          : > DACC          PAGE = 1

   DcanaRegsFile		 : > DCANA,		   PAGE = 1
   DcanbRegsFile		 : > DCANB,		   PAGE = 1

   DcsmRegsZ1File		 : > DCSM_Z1,		   PAGE = 1
   DcsmRegsZ2File		 : > DCSM_Z2,		   PAGE = 1
   DcsmRegsCommonFile	 : > DCSM_COMMON,	   PAGE = 1

   DcsmOtpZ1File		 : > DCSM_OTP_Z1,	   PAGE = 1
   DcsmOtpZ2File		 : > DCSM_OTP_Z2,	   PAGE = 1

   DmaRegsFile           : > DMA           PAGE = 1
   DmaClaSrcSelRegsFile  : > DMACLASRCSEL  PAGE = 1

   ECap1RegsFile         : > ECAP1,        PAGE = 1
   ECap2RegsFile         : > ECAP2,        PAGE = 1
   ECap3RegsFile         : > ECAP3,        PAGE = 1
   ECap4RegsFile         : > ECAP4,        PAGE = 1
   ECap5RegsFile         : > ECAP5,        PAGE = 1
   ECap6RegsFile         : > ECAP6,        PAGE = 1
   
   Emif1RegsFile         : > EMIF1         PAGE = 1
   Emif2RegsFile         : > EMIF2         PAGE = 1

   EPwm1RegsFile         : > EPWM1,        PAGE = 1
   EPwm2RegsFile         : > EPWM2,        PAGE = 1
   EPwm3RegsFile         : > EPWM3,        PAGE = 1
   EPwm4RegsFile         : > EPWM4,        PAGE = 1
   EPwm5RegsFile         : > EPWM5,        PAGE = 1
   EPwm6RegsFile         : > EPWM6,        PAGE = 1
   EPwm7RegsFile         : > EPWM7,        PAGE = 1
   EPwm8RegsFile         : > EPWM8,        PAGE = 1
   EPwm9RegsFile         : > EPWM9,        PAGE = 1
   EPwm10RegsFile        : > EPWM10,       PAGE = 1
   EPwm11RegsFile        : > EPWM11,       PAGE = 1
   EPwm12RegsFile        : > EPWM12,       PAGE = 1

   EPwmXbarRegsFile      : > EPWM_XBAR     PAGE = 1

   EQep1RegsFile         : > EQEP1,        PAGE = 1
   EQep2RegsFile         : > EQEP2,        PAGE = 1
   EQep3RegsFile         : > EQEP3,        PAGE = 1

   FlashCtrlRegsFile     : > FLASH_CTRL    PAGE = 1
   FlashEccRegsFile      : > FLASH_ECC     PAGE = 1

   GpioCtrlRegsFile      : > GPIOCTRL,     PAGE = 1
   GpioDataRegsFile      : > GPIODAT,      PAGE = 1

   GpioOutXbarRegsFile   : > GPIO_OUT_XBAR PAGE = 1
   HwbistRegsFile        : > HWBIST        	PAGE = 1
   I2caRegsFile          : > I2CA,          PAGE = 1
   I2cbRegsFile          : > I2CB,          PAGE = 1
   InputXbarRegsFile     : > INPUT_XBAR     PAGE = 1
   XbarRegsFile          : > XBAR           PAGE = 1
   IpcRegsFile           : > IPC,           PAGE = 1

   RomPrefetchRegsFile       : > ROMPREFETCH,       PAGE = 1
   MemCfgRegsFile            : > MEMCFG,            PAGE = 1
   Emif1ConfigRegsFile       : > EMIF1CONFIG,       PAGE = 1
   Emif2ConfigRegsFile       : > EMIF2CONFIG,       PAGE = 1
   AccessProtectionRegsFile  : > ACCESSPROTECTION,  PAGE = 1
   MemoryErrorRegsFile       : > MEMORYERROR,       PAGE = 1
   RomWaitStateRegsFile      : > ROMWAITSTATE,      PAGE = 1

   McbspaRegsFile        : > MCBSPA,       PAGE = 1
   McbspbRegsFile        : > MCBSPB,       PAGE = 1

   UppRegsFile           : > UPP,          PAGE = 1

   NmiIntruptRegsFile    : > NMIINTRUPT,   PAGE = 1
   PbistRegsFile         : > PBIST,        PAGE = 1
   PieCtrlRegsFile       : > PIE_CTRL,     PAGE = 1

   SciaRegsFile          : > SCIA,         PAGE = 1
   ScibRegsFile          : > SCIB,         PAGE = 1
   ScicRegsFile          : > SCIC,         PAGE = 1
   ScidRegsFile          : > SCID,         PAGE = 1
   
   Sdfm1RegsFile		 : > SDFM1,		   PAGE = 1
   Sdfm2RegsFile		 : > SDFM2,		   PAGE = 1

   SpiaRegsFile          : > SPIA,        PAGE = 1
   SpibRegsFile          : > SPIB,        PAGE = 1
   SpicRegsFile          : > SPIC,        PAGE = 1
   SpidRegsFile          : > SPID,        PAGE = 1

   DevCfgRegsFile        : > DEV_CFG,     PAGE = 1
   ClkCfgRegsFile        : > CLK_CFG,     PAGE = 1
   CpuSysRegsFile        : > CPU_SYS,     PAGE = 1

   TrigRegsFile          : > TRIG,        PAGE = 1

   WdRegsFile            : > WD,          PAGE = 1

   XintRegsFile          : > XINT       PAGE = 1
   MemCfgRegs		     : > MEMCFG     PAGE = 1

	//local c1 memory
   AmtechFile        : > RAMLS0,  	    PAGE = 0
   tim0File		     : > RAMLS0,        PAGE = 0
   ADCFile 		     : > RAMLS0,        PAGE = 0
   DACFile 		     : > RAMLS0,      	PAGE = 0
   c_varsFile_c1 	 : > RAMLS0,	   	PAGE = 0
   svpwm_varsFile 	 : > RAMLS0,	  	PAGE = 0
   autotune_varsFile : > RAMLS0	   	    PAGE = 0

// USED GLOBAL MEMORY IN CPU2
   actFile		     : > RAMGS0,	    PAGE = 1 //common RAM for both CPU MT
   minFile		     : > RAMGS1,	    PAGE = 1
   maxFile		     : > RAMGS2,	    PAGE = 1
   dfltFile  	     : > RAMGS3,	    PAGE = 1
   current2File		: > RAMGS4,	   	PAGE = 1
   current4File		: > RAMGS4,	   	PAGE = 1
   current460File	: > RAMGS4,	   	PAGE = 1
   current5File		: > RAMGS4,	   	PAGE = 1
   current6File		: > RAMGS4,	   	PAGE = 1

   scia_rxFile	     : > RAMGS5,      	PAGE = 1
   scib_rxFile	     : > RAMGS5,      	PAGE = 1
   scic_rxFile	     : > RAMGS5,      	PAGE = 1
   scid_rxFile	     : > RAMGS5,      	PAGE = 1
   scia_txFile	     : > RAMGS5,      	PAGE = 1
   scib_txFile	     : > RAMGS5,      	PAGE = 1
   scic_txFile	     : > RAMGS5,      	PAGE = 1
   scid_txFile	     : > RAMGS5,      	PAGE = 1
   spi_txFile	     : > RAMGS5,      	PAGE = 1
   spi_rxFile	     : > RAMGS5,      	PAGE = 1

   plc_varsFile 	: > RAMGS6,		PAGE = 1
   pid_varsFile 	: > RAMGS6,		PAGE = 1 //37.00.18
   fanFile			: > RAMGS6,	   	PAGE = 1
   pumpFile			: > RAMGS6,	   	PAGE = 1
   conveyorFile		: > RAMGS6,	   	PAGE = 1
   compressorFile	: > RAMGS6,	   	PAGE = 1
   fermentorFile	: > RAMGS6,	   	PAGE = 1
   centrifuseFile	: > RAMGS6,	   	PAGE = 1
   hoistFile		: > RAMGS6,	   	PAGE = 1

   C2ownnedFile		 : > RAMGS7,	   	PAGE = 1 //common RAM for both CPU MT
   c_varsFile_c2 	 : > RAMGS7,	    PAGE = 1	//37.01.00.7.12
   c1toc2_commFile	 : > RAMGS7,	   	PAGE = 1 //MT

// USED GLOBAL MEMORY IN CPU1

   c_varsFile	 	 : > RAMGS8,	   	PAGE = 1
   x24_bitsFile		 : > RAMGS8,	   	PAGE = 1
   foc_varsFile		 : > RAMGS8,		PAGE = 1
   C1ownnedFile		 : > RAMGS8,	   	PAGE = 1 //common RAM for both CPU MT


}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen F2837xD_Headers_nonBIOS_cpu2.txt Download

MEMORY
{
 PAGE 0:    /* Program Memory */

 PAGE 1:    /* Data Memory */

   ADCA_RESULT   : origin = 0x000B00, length = 0x000020
   ADCB_RESULT   : origin = 0x000B20, length = 0x000020
   ADCC_RESULT   : origin = 0x000B40, length = 0x000020
   ADCD_RESULT   : origin = 0x000B60, length = 0x000020

   ADCA          : origin = 0x007400, length = 0x000080
   ADCB          : origin = 0x007480, length = 0x000080
   ADCC          : origin = 0x007500, length = 0x000080
   ADCD          : origin = 0x007580, length = 0x000080

   ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080
   
   CLA1          : origin = 0x001400, length = 0x000040     /* CLA registers */

   CLB_XBAR      : origin = 0x007A40, length = 0x000040

   CMPSS1        : origin = 0x005C80, length = 0x000020
   CMPSS2        : origin = 0x005CA0, length = 0x000020
   CMPSS3        : origin = 0x005CC0, length = 0x000020
   CMPSS4        : origin = 0x005CE0, length = 0x000020
   CMPSS5        : origin = 0x005D00, length = 0x000020
   CMPSS6        : origin = 0x005D20, length = 0x000020
   CMPSS7        : origin = 0x005D40, length = 0x000020
   CMPSS8        : origin = 0x005D60, length = 0x000020

   CPU_TIMER0    : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
   CPU_TIMER1    : origin = 0x000C08, length = 0x000008     /* CPU Timer1 registers */
   CPU_TIMER2    : origin = 0x000C10, length = 0x000008     /* CPU Timer2 registers */

   DACA          : origin = 0x005C00, length = 0x000010
   DACB          : origin = 0x005C10, length = 0x000010
   DACC          : origin = 0x005C20, length = 0x000010

   DCANA         : origin = 0x048000, length = 0x001000		/* DCAN A Registers */
   DCANB         : origin = 0x04A000, length = 0x001000		/* DCAN B Registers */

   DMA          : origin = 0x001000, length = 0x000200
   DMACLASRCSEL : origin = 0x007980, length = 0x000040

   ECAP1        : origin = 0x005000, length = 0x000020     /* Enhanced Capture 1 registers */
   ECAP2        : origin = 0x005020, length = 0x000020     /* Enhanced Capture 2 registers */
   ECAP3        : origin = 0x005040, length = 0x000020     /* Enhanced Capture 3 registers */
   ECAP4        : origin = 0x005060, length = 0x000020     /* Enhanced Capture 4 registers */
   ECAP5        : origin = 0x005080, length = 0x000020     /* Enhanced Capture 5 registers */
   ECAP6        : origin = 0x0050A0, length = 0x000020     /* Enhanced Capture 6 registers */
   
   EMIF1        : origin = 0x047000, length = 0x000800
   EMIF2        : origin = 0x047800, length = 0x000800

   EQEP1        : origin = 0x005100, length = 0x000040     /* Enhanced QEP 1 registers */
   EQEP2        : origin = 0x005140, length = 0x000040     /* Enhanced QEP 2 registers */
   EQEP3        : origin = 0x005180, length = 0x000040     /* Enhanced QEP 3 registers */

   EPWM1        : origin = 0x004000, length = 0x000100     /* Enhanced PWM 1 registers */
   EPWM2        : origin = 0x004100, length = 0x000100     /* Enhanced PWM 2 registers */
   EPWM3        : origin = 0x004200, length = 0x000100     /* Enhanced PWM 3 registers */
   EPWM4        : origin = 0x004300, length = 0x000100     /* Enhanced PWM 4 registers */
   EPWM5        : origin = 0x004400, length = 0x000100     /* Enhanced PWM 5 registers */
   EPWM6        : origin = 0x004500, length = 0x000100     /* Enhanced PWM 6 registers */
   EPWM7        : origin = 0x004600, length = 0x000100     /* Enhanced PWM 7 registers */
   EPWM8        : origin = 0x004700, length = 0x000100     /* Enhanced PWM 8 registers */
   EPWM9        : origin = 0x004800, length = 0x000100     /* Enhanced PWM 9 registers */
   EPWM10       : origin = 0x004900, length = 0x000100     /* Enhanced PWM 10 registers */
   EPWM11       : origin = 0x004A00, length = 0x000100     /* Enhanced PWM 11 registers */
   EPWM12       : origin = 0x004B00, length = 0x000100     /* Enhanced PWM 12 registers */

   EPWM_XBAR  	: origin = 0x007A00, length = 0x000040

   FLASH_CTRL  : origin = 0x05F800, length = 0x000300
   FLASH_ECC   : origin = 0x05FB00, length = 0x000040

   GPIOCTRL     : origin = 0x007C00, length = 0x000180     /* GPIO control registers */
   GPIODAT      : origin = 0x007F00, length = 0x000030     /* GPIO data registers */

   GPIO_OUT_XBAR : origin = 0x007A80, length = 0x000040
   HWBIST       : origin = 0x05E000, length = 0x000100     /* HWBIST registers */
   I2CA         : origin = 0x007300, length = 0x000040     /* I2C-A registers */
   I2CB         : origin = 0x007340, length = 0x000040     /* I2C-B registers */

   IPC          : origin = 0x050000, length = 0x001000

   ROMPREFETCH  : origin = 0x05E608, length = 0x000002

   MEMCFG       : origin = 0x05F400, length = 0x000080     /* Mem Config registers */
   EMIF1CONFIG  : origin = 0x05F480, length = 0x000020     /* Emif-1 Config registers */
   EMIF2CONFIG  : origin = 0x05F4A0, length = 0x000020     /* Emif-2 Config registers */
   ACCESSPROTECTION  : origin = 0x05F4C0, length = 0x000040     /* Access Protection registers */
   MEMORYERROR  : origin = 0x05F500, length = 0x000040     /* Access Protection registers */
   ROMWAITSTATE : origin = 0x05F540, length = 0x000002     /* ROM Config registers */
   

   MCBSPA       : origin = 0x006000, length = 0x000040     /* McBSP-A registers */
   MCBSPB       : origin = 0x006040, length = 0x000040     /* McBSP-A registers */

   NMIINTRUPT   : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */

   PIE_CTRL     : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
   PIE_VECT     : origin = 0x000D00, length = 0x000200     /* PIE Vector Table */
   PBIST        : origin = 0x05E200, length = 0x000200     /* PBIST registers */
   SCIA         : origin = 0x007200, length = 0x000010     /* SCI-A registers */
   SCIB         : origin = 0x007210, length = 0x000010     /* SCI-B registers */
   SCIC         : origin = 0x007220, length = 0x000010     /* SCI-C registers */
   SCID         : origin = 0x007230, length = 0x000010     /* SCI-D registers */
   
   SDFM1		: origin = 0x005E00, length = 0x000080	   /* Sigma delta 1 registers */
   SDFM2		: origin = 0x005E80, length = 0x000080	   /* Sigma delta 2 registers */

   SPIA         : origin = 0x006100, length = 0x000010
   SPIB         : origin = 0x006110, length = 0x000010
   SPIC         : origin = 0x006120, length = 0x000010
   SPID         : origin = 0x006130, length = 0x000010

   UPP          : origin = 0x006200, length = 0x000100     /* uPP registers */

   DEV_CFG     : origin = 0x05D000, length = 0x000180
   CLK_CFG     : origin = 0x05D200, length = 0x000100
   CPU_SYS     : origin = 0x05D300, length = 0x000100

   INPUT_XBAR   : origin = 0x007900, length = 0x000020
   XBAR         : origin = 0x007920, length = 0x000020
   TRIG         : origin = 0x007940, length = 0x000010
   WD           : origin = 0x007000, length = 0x000040

   XINT         : origin = 0x007070, length = 0x000010

   DCSM_Z1      : origin = 0x05F000, length = 0x000030     /* Zone 1 Dual code security module registers */
   DCSM_Z2      : origin = 0x05F040, length = 0x000030     /* Zone 2 Dual code security module registers */
   DCSM_COMMON  : origin = 0x05F070, length = 0x000010     /* Common Dual code security module registers */

   DCSM_OTP_Z1  : origin = 0x078800, length = 0x000020     /* Part of Z1 OTP.  LinkPointer/JTAG lock/ Boot Mode */
   DCSM_OTP_Z2  : origin = 0x078900, length = 0x000020     /* Part of Z2 OTP.  LinkPointer/JTAG lock */
}


SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
  UNION run = PIE_VECT, PAGE = 1
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

   AdcaResultFile        : > ADCA_RESULT,  PAGE = 1
   AdcbResultFile        : > ADCB_RESULT,  PAGE = 1
   AdccResultFile        : > ADCC_RESULT,  PAGE = 1
   AdcdResultFile        : > ADCD_RESULT,  PAGE = 1

   AdcaRegsFile          : > ADCA,         PAGE = 1
   AdcbRegsFile          : > ADCB,         PAGE = 1
   AdccRegsFile          : > ADCC,         PAGE = 1
   AdcdRegsFile          : > ADCD,         PAGE = 1

   AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1
   
   Cla1RegsFile          : > CLA1,         PAGE = 1
   Cla1SoftIntRegsFile   : > PIE_CTRL, 	   PAGE = 1, type=DSECT

   ClbXbarRegsFile      : > CLB_XBAR     PAGE = 1

   Cmpss1RegsFile        : > CMPSS1,      PAGE = 1
   Cmpss2RegsFile        : > CMPSS2,      PAGE = 1
   Cmpss3RegsFile        : > CMPSS3,      PAGE = 1
   Cmpss4RegsFile        : > CMPSS4,      PAGE = 1
   Cmpss5RegsFile        : > CMPSS5,      PAGE = 1
   Cmpss6RegsFile        : > CMPSS6,      PAGE = 1
   Cmpss7RegsFile        : > CMPSS7,      PAGE = 1
   Cmpss8RegsFile        : > CMPSS8,      PAGE = 1

   CpuTimer0RegsFile     : > CPU_TIMER0,    PAGE = 1
   CpuTimer1RegsFile     : > CPU_TIMER1,    PAGE = 1
   CpuTimer2RegsFile     : > CPU_TIMER2,    PAGE = 1

   DacaRegsFile          : > DACA          PAGE = 1
   DacbRegsFile          : > DACB          PAGE = 1
   DaccRegsFile          : > DACC          PAGE = 1

   DcanaRegsFile		 : > DCANA,		   PAGE = 1
   DcanbRegsFile		 : > DCANB,		   PAGE = 1

   DcsmRegsZ1File		 : > DCSM_Z1,		   PAGE = 1
   DcsmRegsZ2File		 : > DCSM_Z2,		   PAGE = 1
   DcsmRegsCommonFile		 : > DCSM_COMMON,	   PAGE = 1

   DcsmOtpZ1File		 : > DCSM_OTP_Z1,	   PAGE = 1
   DcsmOtpZ2File		 : > DCSM_OTP_Z2,	   PAGE = 1

   DmaRegsFile           : > DMA           PAGE = 1
   DmaClaSrcSelRegsFile  : > DMACLASRCSEL  PAGE = 1

   ECap1RegsFile         : > ECAP1,        PAGE = 1
   ECap2RegsFile         : > ECAP2,        PAGE = 1
   ECap3RegsFile         : > ECAP3,        PAGE = 1
   ECap4RegsFile         : > ECAP4,        PAGE = 1
   ECap5RegsFile         : > ECAP5,        PAGE = 1
   ECap6RegsFile         : > ECAP6,        PAGE = 1
   
   Emif1RegsFile         : > EMIF1         PAGE = 1
   Emif2RegsFile         : > EMIF2         PAGE = 1

   EPwm1RegsFile         : > EPWM1,        PAGE = 1
   EPwm2RegsFile         : > EPWM2,        PAGE = 1
   EPwm3RegsFile         : > EPWM3,        PAGE = 1
   EPwm4RegsFile         : > EPWM4,        PAGE = 1
   EPwm5RegsFile         : > EPWM5,        PAGE = 1
   EPwm6RegsFile         : > EPWM6,        PAGE = 1
   EPwm7RegsFile         : > EPWM7,        PAGE = 1
   EPwm8RegsFile         : > EPWM8,        PAGE = 1
   EPwm9RegsFile         : > EPWM9,        PAGE = 1
   EPwm10RegsFile        : > EPWM10,       PAGE = 1
   EPwm11RegsFile        : > EPWM11,       PAGE = 1
   EPwm12RegsFile        : > EPWM12,       PAGE = 1

   EPwmXbarRegsFile      : > EPWM_XBAR     PAGE = 1

   EQep1RegsFile         : > EQEP1,        PAGE = 1
   EQep2RegsFile         : > EQEP2,        PAGE = 1
   EQep3RegsFile         : > EQEP3,        PAGE = 1

   FlashCtrlRegsFile     : > FLASH_CTRL    PAGE = 1
   FlashEccRegsFile      : > FLASH_ECC     PAGE = 1

   GpioCtrlRegsFile      : > GPIOCTRL,     PAGE = 1
   GpioDataRegsFile      : > GPIODAT,      PAGE = 1

   GpioOutXbarRegsFile    : > GPIO_OUT_XBAR    PAGE = 1
   HwbistRegsFile        : > HWBIST        PAGE = 1
   I2caRegsFile          : > I2CA,          PAGE = 1
   I2cbRegsFile          : > I2CB,          PAGE = 1
   InputXbarRegsFile     : > INPUT_XBAR     PAGE = 1
   XbarRegsFile          : > XBAR           PAGE = 1
   IpcRegsFile           : > IPC,           PAGE = 1

   RomPrefetchRegsFile       : > ROMPREFETCH,       PAGE = 1
   MemCfgRegsFile            : > MEMCFG,            PAGE = 1
   Emif1ConfigRegsFile       : > EMIF1CONFIG,       PAGE = 1
   Emif2ConfigRegsFile       : > EMIF2CONFIG,       PAGE = 1
   AccessProtectionRegsFile  : > ACCESSPROTECTION,  PAGE = 1
   MemoryErrorRegsFile       : > MEMORYERROR,       PAGE = 1
   RomWaitStateRegsFile      : > ROMWAITSTATE,      PAGE = 1

   McbspaRegsFile        : > MCBSPA,       PAGE = 1
   McbspbRegsFile        : > MCBSPB,       PAGE = 1

   UppRegsFile           : > UPP,       PAGE = 1

   NmiIntruptRegsFile    : > NMIINTRUPT,   PAGE = 1
   PbistRegsFile         : > PBIST,        PAGE = 1
   PieCtrlRegsFile       : > PIE_CTRL,     PAGE = 1

   SciaRegsFile          : > SCIA,         PAGE = 1
   ScibRegsFile          : > SCIB,         PAGE = 1
   ScicRegsFile          : > SCIC,         PAGE = 1
   ScidRegsFile          : > SCID,         PAGE = 1
   
   Sdfm1RegsFile		 : > SDFM1,		   PAGE = 1
   Sdfm2RegsFile		 : > SDFM2,		   PAGE = 1

   SpiaRegsFile          : > SPIA,        PAGE = 1
   SpibRegsFile          : > SPIB,        PAGE = 1
   SpicRegsFile          : > SPIC,        PAGE = 1
   SpidRegsFile          : > SPID,        PAGE = 1

   DevCfgRegsFile        : > DEV_CFG,     PAGE = 1
   ClkCfgRegsFile        : > CLK_CFG,     PAGE = 1
   CpuSysRegsFile        : > CPU_SYS,     PAGE = 1

   TrigRegsFile          : > TRIG,         PAGE = 1

   WdRegsFile            : > WD,           PAGE = 1


   XintRegsFile          : > XINT          PAGE = 1
   MemCfgRegs		     : > MEMCFG        PAGE = 1

	//cpu2 local
	tim0File		     : > RAMLS0,      	PAGE = 0
	CPU2_CLA2_File		 : > RAMLS0,      	PAGE = 0	//37.01.00.7.12

// USED GLOBAL MEMORY IN CPU2

   actFile		     : > RAMGS0,	   		PAGE = 1 //common RAM for both CPU MT
   minFile		     : > RAMGS1,	   		PAGE = 1
   maxFile		     : > RAMGS2,	   		PAGE = 1
   dfltFile  	     : > RAMGS3,	   		PAGE = 1
   current2File		: > RAMGS4,	   	PAGE = 1
   current4File		: > RAMGS4,	   	PAGE = 1
   current460File	: > RAMGS4,	   	PAGE = 1
   current5File		: > RAMGS4,	   	PAGE = 1
   current6File		: > RAMGS4,	   	PAGE = 1

   scia_rxFile	     : > RAMGS5,      	PAGE = 1
   scib_rxFile	     : > RAMGS5,      	PAGE = 1
   scic_rxFile	     : > RAMGS5,      	PAGE = 1
   scid_rxFile	     : > RAMGS5,      	PAGE = 1
   scia_txFile	     : > RAMGS5,      	PAGE = 1
   scib_txFile	     : > RAMGS5,      	PAGE = 1
   scic_txFile	     : > RAMGS5,      	PAGE = 1
   scid_txFile	     : > RAMGS5,      	PAGE = 1
   spi_txFile	     : > RAMGS5,      	PAGE = 1
   spi_rxFile	     : > RAMGS5,      	PAGE = 1

   plc_varsFile 	: > RAMGS6,		PAGE = 1
   pid_varsFile 	: > RAMGS6,		PAGE = 1 //37.00.18
   fanFile			: > RAMGS6,	   	PAGE = 1
   pumpFile			: > RAMGS6,	   	PAGE = 1
   conveyorFile		: > RAMGS6,	   	PAGE = 1
   compressorFile	: > RAMGS6,	   	PAGE = 1
   fermentorFile	: > RAMGS6,	   	PAGE = 1
   centrifuseFile	: > RAMGS6,	   	PAGE = 1
   hoistFile		: > RAMGS6,	   	PAGE = 1
   C2ownnedFile		 : > RAMGS7,	   	PAGE = 1 //common RAM for both CPU MT
   c_varsFile_c2 	 : > RAMGS7,	    PAGE = 1	//37.01.00.7.12
   c1toc2_commFile	 : > RAMGS7,	   	PAGE = 1 //MT

// USED GLOBAL MEMORY IN CPU1
   c_varsFile	 	 : > RAMGS8,	PAGE = 1
   x24_bitsFile		 : > RAMGS8,	PAGE = 1
   C1ownnedFile		 : > RAMGS8,	PAGE = 1 //common RAM for both CPU MT
   foc_varsFile		 : > RAMGS8,	PAGE = 1
}

0 Delaney Woodward 5 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

Allow me a few days to look into this and I will get back to you.

Best Regards,

Delaney

0 Amtech 5 months ago in reply to Delaney Woodward

Genius 4585 points

Waiting for your reply

0 Delaney Woodward 5 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

Tp update, I still haven't had a chance to look into your settings but will try to in the next couple of days.

Best Regards,

Delaney

0 Amtech 5 months ago in reply to Delaney Woodward

Genius 4585 points

Hi,

Delaney

Any other information are required for further investigation?

I had carried out lot of try but not reaching in conclude stage and why it is happening.

Waiting for your help.

Regards,

Amtech

0 Delaney Woodward 5 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

No more information is needed; I have just been held up with other activities and haven't had a chance to look into this. I will hopefully get to this by the end of this week. I apologize for the delay.

Best Regards,

Delaney

0 Amtech 4 months ago in reply to Delaney Woodward

Genius 4585 points

Hi,

Delaney

If you have busy schedule than you transfer my query to other relevant expert because i have struggling for last 15-16 days.

I have to solve in urgent basis because problem in our running product.

Any other information are required for further investigation?

Waiting for your help.

Regards,

Amtech

0 Delaney Woodward 4 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

I will see if another expert is able to look into this more for you. I apologize for the delay.

I will say, if you have any specific questions, we would be able to answer these more quickly. Looking through code implementations usually takes some more time for us to help with and is why I haven't been able to devote time to this yet. If you have any suspicions about what the issue could be from your debugging that you want to ask about, that would probably be more productive.

Best Regards,

Delaney

0 Amtech 4 months ago in reply to Delaney Woodward

Genius 4585 points

Hi,

Delaney

If it is possible to check attached memory map, cmd and Headers nonbios of working and non working files are "ok" or "not ok".

Waiting for your reply.

Regards,

Amtech

0 Delaney Woodward 4 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

I should finally have time to look into this tomorrow. Thank you for your patience.

Best Regards,

Delaney

0 Delaney Woodward 4 months ago in reply to Delaney Woodward

TI__Mastermind 20990 points

Hello,

I sincerely apologize for the long delay. I have looked through the files you provided and have concluded that the issue should not be related to the linker placement of the memory since the CPU2 CLA memory elements are allocated to the exact same memory locations in both cases. Further, if the only change is in Flash E, the CLA does not have access to this memory at all and should not be affected by this change from a memory POV. The functionality of the added code must be interfering somehow.

A couple follow up questions:

Are you using CLA math at all on CPU2 CLA? If so, are you using the tables in ROM or loading your own into the LSRAM?
If you add a breakpoint instruction to the CLA task doing the Modbus operation, is it getting hit? It would be helpful to narrow down what exactly in the code is getting broken - which instruction does it fail at?
What resources are being accessed by the new code you added (ex. if there are variables being accessed, please provide the names)?

Best Regards,

Delaney

0 Amtech 4 months ago in reply to Delaney Woodward

Genius 4585 points

Hi,

Delaney

Thanks for your kind reply.

Regarding to above questions,

1) Are you using CLA math at all on CPU2 CLA? If so, are you using the tables in ROM or loading your own into the LSRAM?

- We are not using CLA math.

2) If you add a breakpoint instruction to the CLA task doing the Modbus operation, is it getting hit? It would be helpful to narrow down what exactly in the code is getting broken - which instruction does it fail at?

- In our context, If our program run in debug mode , MODBUS TCP-IP functionality is working fine. we are facing issue in standalone mode.

3) What resources are being accessed by the new code you added (ex. if there are variables being accessed, please provide the names)?

- Only Flash E code change.(FLASHE used memory is 0001231d for non working program and 00012311d for working program)

- Due to this change in ENTRY POINT SYMBOL: "_c_int00" address: 00099e99 (For non working code) and "_c_int00" address: 00099e8d(Working code).

Regards,

Amtech

0 Delaney Woodward 4 months ago in reply to Amtech

TI__Mastermind 20990 points

Hello,

I see, instead of a breakpoint in the CLA task in debugger mode, can you try toggling some GPIOs around each line of the CLA task so we can see where it is getting stuck when in standalone mode? You can use an oscilloscope on those pins to see where the code gets to.

To clarify also, you are saying that the only difference between the working and non-working project are the flash entry point? Does other functionality in your project other than the Modbus TCP-IP functionality still work in the errored project?

Best Regards,

Delaney

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