TMS320F2800157-Q1: Application issues.

Reed

Expert 2080 points

Tool/software:

Hi team,

F2800157QPMRQ1 is used as the main control chip, and TPS3836K33DBVR is used as the voltage monitor. I am currently facing a problem that requires assistance in resolving:

The test found that the SCI mode boot cannot be burned. After powering on, manually lower the reset signal DSP-REET once or pull the reset chip CT signal to 3.3V or 4V before normal burning can be achieved. It is judged that the reset signal is not at a low level for enough time to burn. But the typical value for the reset signal to be at a low level after power on written in the DSP specification is 100us. After actual testing, after connecting four reset chips in series (CT=GND, each chip has a 10ms delay), DSP-REET can burn and boot normally with a 40ms delay relative to VDD.

The following figure shows the specifications of the reset chip regarding output delay (when CT=VDD, the output is delayed by 200ms relative to VDD)

DSP specification sheet explains the delay of reset signal relative to VDD.

6 months ago

0 Prarthan Bhatt 6 months ago

TI__Genius 14926 points

Hi,

I can't understand what the question is here.

Why can't you power-on chip and flash program, why is MCU reset is required ?

Reed said:
After powering on, manually lower the reset signal DSP-REET once or pull the reset chip CT signal to 3.3V or 4V before normal burning can be achieved.

The reset signal is active low, meaning the device is in normal state when pulled up (3.3V). I cant understand what you mean by below ? "Low level is not enough to burn ?"

Reed said:
It is judged that the reset signal is not at a low level for enough time to burn

Can you show diagram of the this connection what do you mean by four chips in series ?

Reed said:
after connecting four reset chips in series

Thanks

0 Reed 6 months ago in reply to Prarthan Bhatt

Expert 2080 points

Hi Prarthan Bhatt,
Thank you for your reply,

Usually, tw (RSL1) can work normally with a delay of 10ms.

My current problem is that in SCI mode, when burning the boot ROM, if there is a delay of 10ms, the burning will encounter errors. However, in actual testing, a delay of more than 30ms is required for success.

Is this phenomenon normal?

0 Prarthan Bhatt 6 months ago in reply to Reed

TI__Genius 14926 points

Hi,

Seems like the issue is only related to SCI boot mode ?

Reed said:
when burning the boot ROM, if there is a delay of 10ms, the burning will encounter errors

What issues are encountered with 10ms of delay.

RSL is fixed time from when supply are stable to when XRsn comes up and I cant understand why this time affects SCI mode or why longer time is required for SCI boot mode.

can you explain how you extended that time to be 30msec ?

Thanks

0 Rong chang Wu 6 months ago in reply to Prarthan Bhatt

Prodigy 10 points

The problem is like this:

I used F2800157QPMRQ1 is used as the main control chip, The TPS3836K33DBVR, as a voltage monitor, outputs a reset signal to the main control chip(The reset time is configured as 10ms).When I select the SCI programming mode(GPIO24=0,GPIO32=1), I find that the programming APP shows a communication connection failure.

I found that SCI programming could be performed after trying to change the reset time to 40ms.

I want to figure out why the SCI communication connection fails when the reset time is 10ms?

0 Ethan Tian 6 months ago in reply to Prarthan Bhatt

TI__Intellectual 1872 points

Hello Prathan

I checked the customer's schematic diagram and didn't find any major issues. You can take another look.

In addition, attached the customer's timing test result.

2800157 Reset Signal.xlsx

0 Ethan Tian 6 months ago in reply to Prarthan Bhatt

TI__Intellectual 1872 points

Hi Prarthan

Any update?

0 Vivek Singh 6 months ago in reply to Ethan Tian

TI__Guru** 115931 points

Hi Ethan,

Prarthan is out this week.

As per our device datasheet, 10ms reset time should be good enough for device to boot properly. In SCI boot, device is reading the data from outside. Have you checked the timing of external device to make sure it's ready to work with F2800157QPMRQ1 when it start early (10ms) ?

Vivek Singh

0 Ethan Tian 5 months ago in reply to Vivek Singh

TI__Intellectual 1872 points

Hi Vivek

Thanks for your reply, please check this file

Ethan Tian said:
2800157 Reset Signal.xlsx

We are checking bootrom now, I will update the test result once the test is finished

0 Ethan Tian 5 months ago in reply to Vivek Singh

TI__Intellectual 1872 points

Hi Vivek

We ran the bootrom and it entered in waitboot. It seems possibly because it fails to recognize the bootmode pin, or is it due to some other reason? However, I have provided the pin levels during the reset period in the Excel file, and the power-up is stable. This issue has been pending for a long time; could you please help check it as soon as possible?

0 Vivek Singh 5 months ago in reply to Ethan Tian

TI__Guru** 115931 points

Ethan,

In this waveform, is Green signal is reset ? If yes then pins should be driven to proper boot value before XRSn is released. Generally it should be pull-up (or pull-down) on bootmode pins to drive it to correct value.

Vivek Singh

0 Ethan Tian 5 months ago in reply to Vivek Singh

TI__Intellectual 1872 points

Vivek

I have already written it in the table. Red: reset signal, yellow: GPIO24, green: GPIO32.

0 Vivek Singh 5 months ago in reply to Ethan Tian

TI__Guru** 115931 points

Ok. Your table snapshot did not show this info. Look like it is capturing only partial info. Are you capturing this waveform while running the BOOTROM with CCS connected ? If yes then please make sure you are setting the emulation boot correctly.

Vivek Singh

0 Ethan Tian 5 months ago in reply to Vivek Singh

TI__Intellectual 1872 points

Hi Vivek

Please see this waveform excel3000.2800157 Reset Signal.xlsx

Customer used the default boot mode pin, GPIO24 and GPIO32, so I think we don't need to check BOOTPIN_CONFIG, right? What need to check to make sure the emulation boot is correct?

Ethan