TMS320F28377D: Is a 32bit access to an 8bit external bus atomic?

Another question is, when accessing two consecutive 32bit registers on the external bus, is the CS activated / deactivated for each 32bit operation, or only once?

Hi Antonio,

I am a bit confused by the wording of your questions. Is the F2837x accessing the FPGA's registers? If yes, over what interface?

In the mean time, I am sending along some links for your reference.

https://software-dl.ti.com/C2000/docs/optimization_guide/phase1/misc.html#atomic-access

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1088500/tms320f28384s-atomic-operations-of-c28x-and-cm4

Thanks,

Sira

Thanks for the answer, and sorry if I was not clear enough.

The FPGA is attached on the EMIF bus as an asynchronous device with an 8bit wide data bus.

In the FPGA there are several 32bit registers mapped on the DSP memory space.

I would like to generate an acknowledge when one of this 32bit register has been read.

I am thinking of checking if all 4 bytes of the 32bit word are accessed while the CS is low, and if so when the CS goes high I will generate the acknowledge signal.

My worry is that the CS goes low once for every byte read, or the CS goes low for two byte access, then the operation is halted to service an higher priority task, then the other two bytes are accessed.

I hope this clarify what I want to do.

Regards

Antonio,

Sorry for the delayed reply. I feel like I need some other experts to comment here. I've reached out to a few.

Thanks,

Sira

Hi Antonio,

For accessing the async memory (SRAM or Flash), the CS pin is asserted only during access to the memory. The CS is de-asserted after byte read or write, then re-asserted during next byte read/write.

If the EMIF supports page mode read for async memory, the CS will keep asserted during the page read.

Dear QJ,

Thanks for the answer.

I see no page size setting or mentioning in the EMIF chapter about async memory, I then assume that is not supported and every byte will have its own cs low/high transition.