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TMS320F2800157: Issue of wireless EFT fail

Leo Wu
Intellectual 1410 points
Part Number: TMS320F2800157


Tool/software:

Hi experts,

My customer is do wireless EFT on F2800157 as the follow picture:

The pulse generating coil is perpendicular to the card

The pulse generating coil is parallel to the card

The pulse amplitude inside the coil is ±3kV. The pulse generation method complies with IEC61000-4-4.

The distance between the coil and the card changes back and forth between 1cm and 10cm. Customer find that When the coil is 1cm away from the chip, the CPU will freeze and be reset by the watchdog.

For the this EFT is wireless and there is no electrical contact between the coil and the card, I have some question:

1. Do we have a radiation tolerance test report for this chip?

2. For this case, is it necessary to add a metal shield to the chip? 

3. Does BU have some suggestions about why the chip will freeze in this test?

PS: Customer feedback that the same test on F28027 is pass. Is the difference in chip manufacturing process between 28027 and 2800157 related to this issue?

Thanks,

Leo

  • 0
    TI__Guru* 80640 points

    Leo,

    I would refer to this section of the DS, and then ask customer to cross reference with their PCB design.  If any of the GPIOs listed in this table see a negative voltage(which is out of spec per the DS), then it could cause the device to go into reset.  It should not stay in reset, unless this voltage persists.

    https://www.ti.com/document-viewer/TMS320F2800157/datasheet#GUID-D36A0056-3934-4395-AED2-9F3C2CCD1C14/TITLE-SPRSP45TOCWRAPPER_SPECIFICATIONS

    Also I would point to this errata: 

    https://www.ti.com/document-viewer/lit/html/SPRZ507D#GUID-C88BE266-4E5C-4A5C-92B9-BE1871E199D9/TITLE-SPRZ466SPRZ4122012

    Customer also needs to look at this as well in this case.

    All the above could be caused by EMC, if the EMC is coupling in such a way that drives our MCU pins out of specification.  

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Intellectual 1410 points

    Hi Matthew,

    Sorry for delay. I spent some time with the customer to confirm the test results.
    We found that the NMI flag was an ECC uncorrectable error. I think it is likely that interference caused multiple bit flips in RAM or FLASH. Customers reported that the previous generation C2000 such as F28027 can pass this test. Is this because the third generation C2000 uses a 65nm process, which has weaker anti-interference ability than the old process?

    Thanks,

    Leo

  • 0 in reply to Leo Wu
    TI__Guru* 80640 points

    Leo,

    Thanks for the update, I think we need to perform more debug before we can draw a final conclusion

    It could be an issue of detection vs one of more robust process.

    The F28027 device did not have ECC or parity protection on any memories, including SRAMs.  So if there was a bit flip, there would be no way to detect it unless it impacted program execution.  I think it is likely SRAM if it is impacted by EMC testing, but we need to verify the address

    1. Is the ECC failure address that is logged for ECC fail, coming from RAM or FLASH address that holds code or data?
    2. Is it always the same address or region of memory?

    Let's assume it is an issue of robustness, i.e. F28027 did not have any impact to its memories during EMC testing, but F280013x does.

    Keep in mind that the core voltage of the F280013x is 1.2V vs 1.8V in the F28027.  So we potentially have less margin if the EMC testing is causing enough noise on the VDD/core supply to droop the supply.  SRAM is fed from core supply alone, so the above memory verification will tell us if this is the more likely cause.  I wouldn't expect flash to be impacted with VDD as much as SRAM.

    1. Is customer using internal VREG or external VDD supply? 
    2. Can customer look at the supply during EMC testing to see if there is any interference during the testing that is causing the supply to go out of spec? 
    3. Can customer also comment on the location and size of decap(s) on the VDD net of the PCB?
    4. Can customer scope XRSn line to make sure it is stable during EMC testing?
    5. Can customer comment on the clock source for the MCU, and even if internal oscillator, what is routed to GPIO19 pin.

    Best,

    Matthew