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TMS320F2800157-Q1: Continuous SOC sampling will cause the sampling results to interfere with each other

Leo Wu
Intellectual 1410 points
Part Number: TMS320F2800157-Q1
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi experts,

My customer AIWIN meet the issue that if they trigger SOC continuously, the ADC sampling result will fluctuate on F2800154.

I try to reproduce the issue on 2800157 launchpad based on demo "adc_ex1_soc_software"

The configuration of ADCA SOC are as follow:

SOC0--A10--sample DACA (the DAC is on another board) output, the DAC output will change between 0.35-3.2V

SOC1--A5--sample DACB (the DAC is on another board) output, the DAC output will fix in 1.65V

SOC2--A0--sample GND

SOC3--A7--sample 3.3V

SOC4--A9--sample GND

The test results are as follows:

1. SOC trigger cycle is 0-1-2-3-4. The result of SOC1 will It will fluctuate between 2000 and 2100

2. I try to change the sample window from 75ns to 750ns and SOC trigger cycle is 0-1-2-3-4. The result of SOC1 will fix at 2048.

3. I try to change the A10 sample source to a fix value and SOC trigger cycle is 0-1-2-3-4. The result of SOC1 will fix at 2048.

4. I try to change the SOC trigger cycle to 0-2-3-4-1. The result of SOC1 will fix at 2000

 

Why does the sampling change data of one SOC affect the results of another SOC？Is there any other improvement method besides extending the sampling time window?

Thanks,

Leo

  • 0
    TI__Mastermind 38290 points

    Hi Leo,

    On the two DAC boards, can you provide what the output circuit of the DAC looks like?  Is there an RC network and if so, what are the values?

    Thanks,

    Joseph 

  • 0 in reply to Joseph Casuga
    TI__Intellectual 1410 points

    Hi Joseph,

    ADC test is on the 2800157 EVM, and DACs are from 280039 EVM.

    On customer side, SOC0 samples the changing voltage value and SOC1-4 sample the fixed voltage value. So, I use changing output from DACA and fixed output from DACB to reproduce the issue which customer meet.

    Thanks,

    Leo

  • 0 in reply to Joseph Casuga
    TI__Intellectual 1410 points

    Hi Joseph,

    Any update?

    Thanks,

    Leo

  • 0 in reply to Leo Wu
    TI__Mastermind 38290 points

    Hi Leo,

    This could be a case of coupling where previous SOC sampling has not been given enough time to sample the signal.  For the experiment you ran using the DAC, the SH register is just not enough to accurately sample the signal because of the DAC impedance.  C2000 DAC has a 5K impedance and 100pF on the buffer.  You can try using the Sample Time Calculator in Sysconfig to show the impact of the DAC impedance on SH acquisition time.  Enter the DAC impedance as 5Kohms and output capacitance as 100pF.  Calculator will show that SH time required is ~4.2uS.  You increased the SH in your experiment by 10x but that is still not enough time.

    In customer's case, what are the impedances on the sources used for the SOCs?  We can do the analysis with the Sample Time Calculator.

    Regards,

    Joseph