Part Number: TMS320F28P650DK
Tool/software:
Hello Team,
I am designing the voltage monitoring circuit which outputs to a CPU ADC in differential mode.
The Figure in the data sheet includes a statement of "Vin Common Mode limitation" it can be interpreted that "Vin common mode" must be less than VREFHI/2 ± 50mV. My understanding is that the conversion range (16-bit Differential) is from VREFLO to VREFHI, hence ADCINxP and ADCINxN both can be from VREFLO to VREFHI and the actual input voltage range (ADCINxP - ADCINxN) is about VREFHI - VREFLO. What is the "Vin Common Mode" in detail, how does it impact the input? (I found about this topic in related threads, but I could not fully clear up my question.)
Thanks.

