TMS320F280037C: ADC linearity question

Hi Johnny,

Please find the answers below:

Johnny Chen said:

(1). They do ADC conversion, would the converted digital result still be linear when sampling voltage is less than 0.1V ? 

Since they sample an analog input voltage which is less than 30mV, the converted digital result doesn't seem to get the value from analog to 12-bit Digital Formula.

We should be able to sample 30mV, expected ADC code = 30m/2.5 (VREFHI-VREFLO=2.5V)  *4096 ==>  ~50LSB 

Though the expectation is the system is clean from any noise sources.

As the input that customer is supply is low and close to VREFLO/ Ground (<0.1V)==> 0 ,  ground noise will affect this. 

Johnny Chen said:

(2). Is there a characteristic representing ADC sampling linearity ?

The ADC is linear for the full range of VREF. the spec mentioned in datasheet is for full range.

we don't have any graph for ADC input vs ADC code though. 

Johnny Chen said:

(3). What's the min. effective sampling voltage for the device ? 

We can use the SNR spec for the ADC to find this. 70.5dB SNR ==> Vmin ~ 800uV ( 70dB --> 316uV & vmin = 316uV *2.5 [considering 2.5V as reference] ). 

800uV is the expected min voltage that the ADC can sense, here the system noise would be minimum. 

If we have a rough idea on the system noise (Application board) then that would be the minimum voltage the ADC can sense in that system. 

Thanks,

Nilesh

Hi Nilesh,

Thanks for your prompt input.

My customer is selecting internal VREFHI = 1.65 V (0 to 3.3 V range) as ADC reference voltage.

Nilesh Khanna said:

We should be able to sample 30mV, expected ADC code = 30m/2.5 (VREFHI-VREFLO=2.5V)  *4096 ==>  ~50LSB 

(1). What is the spec. basis / evidence to know we are able to sample 30mV ? I assume you are based on the expected ADC code > INL / DNL error ? 

(2). For internal VREFHI = 1.65 V (0 to 3.3 V range), the denominator of the formula, I should have input voltage divided by 3.3 * 4096, right ? 

Nilesh Khanna said:

800uV is the expected min voltage that the ADC can sense

How do you get the 800uV (70.5dB SNR) & 316uV (70dB) for expected min voltage ? Is it specified in the DS ? 

Thanks and regards,

Johnny

Hi Johnny,

Johnny Chen said:

How do you get the 800uV (70.5dB SNR) & 316uV (70dB) for expected min voltage ? Is it specified in the DS ? 

I had just converted SNR to noise in voltage(316mV) and added it to the LSB size(600uV) considering 2.5V as reference. 

Nilesh Khanna said:

We can use the SNR spec for the ADC to find this. 70.5dB SNR ==> Vmin ~ 800uV ( 70dB --> 316uV & vmin = 316uV *2.5 [considering 2.5V as reference] ).

For 3.3V reference --> 316uV +800uV ==>  ~ 1.1mV .

Johnny Chen said:

(1). What is the spec. basis / evidence to know we are able to sample 30mV ? I assume you are based on the expected ADC code > INL / DNL error ?

We can use the offset spec as well to determine that +/- 5LSB

Thanks,

Nilesh