Part Number: TMS320F28388D
Tool/software:
void DriverPwm_SetupEpwm(void) {
// EPWM should work at full 200MHz speed
EALLOW;
ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV=0U;
EDIS;
// Inverter: centered aligned -> Modulo: SYSCLKOUT/PWM_FREQ/2
dp_inv_period = (uint16_t)roundf(((float)SYSCLKOUT) / DP_INV_FREQ_DEFAULT) / 2;
// Deadtime
float dt=((float)PWM_DEADTIME_DEFAULT)*1.0e-9;
float ton=((float)PWM_TON_MIN)*1.0e-9;
dp_deadtime_tick = (uint16_t)(((float)SYSCLKOUT)*dt);
dp_Tonmin_tick = (uint16_t)(((float)SYSCLKOUT)*ton);
dp_deadtime_Tonmin_tick=dp_deadtime_tick+dp_Tonmin_tick;
// Rho limits (edge aligned)
dp_rho_min=((float)(dp_deadtime_Tonmin_tick))/((float)dp_inv_period);
dp_rho_max=1.0f-dp_rho_min;
// configure channels
for (uint16_t i=0; i<DP_INV_CH_N; i++) {
/*
* TIME BASE
*/
// first channel is SYNC master
bool master = (i==0);
// TBCTL (time base control)
// CTRMODE=2 (Up/down counting)
// PHSEN=Off/On
// PRDLD=0 (Shadow loading)
// SWFSYNC=0 (No forcing)
// HSPCLKDIV=0 (DIV1)
// CLKDIV=0 (DIV1)
// PHSDIR=0/1 (Count up/down after sync: depends on phase - see later)
// FREE_SOFT=0 (Stop on debugger break)
dp_inv_ch[i]->TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
if (master) {
dp_inv_ch[i]->TBCTL.bit.PHSEN = 0;
}
else {
dp_inv_ch[i]->TBCTL.bit.PHSEN = 1;
}
dp_inv_ch[i]->TBCTL.bit.PRDLD = TB_SHADOW;
dp_inv_ch[i]->TBCTL.bit.SWFSYNC = 0;
dp_inv_ch[i]->TBCTL.bit.HSPCLKDIV = TB_DIV1;
dp_inv_ch[i]->TBCTL.bit.CLKDIV = TB_DIV1;
dp_inv_ch[i]->TBCTL.bit.PHSDIR = 0;
dp_inv_ch[i]->TBCTL.bit.FREE_SOFT = 0;
// period
dp_inv_ch[i]->TBPRD = dp_inv_period; // see figure 26-6 SPRUI0B
// sync:
// - Master (first): enable sync out
// - Slave (others): enable sync in
if (master) {
dp_inv_ch[i]->EPWMSYNCOUTEN.bit.ZEROEN=1U;
}
else {
#if defined(HW_EVB_F28388)
dp_buck_ch[i]->EPWMSYNCINSEL.bit.SEL=SYNC_IN_SRC_SYNCOUT_EPWM7;
#elif defined(HW_SF1220_PROTOA)
dp_buck_ch[i]->EPWMSYNCINSEL.bit.SEL=SYNC_IN_SRC_SYNCOUT_EPWM10;
#elif defined (HW_LOC381_0_SINGLECORE) || defined (HW_LOC381_0_DOUBLECORE) || defined (HW_LOC392_1_DOUBLECORE)
dp_inv_ch[i]->EPWMSYNCINSEL.bit.SEL=SYNC_IN_SRC_SYNCOUT_EPWM8;
#endif
}
// initial phase
dp_inv_ch[i]->TBPHS.bit.TBPHS=0;
dp_inv_ch[i]->TBCTL.bit.PHSDIR=TB_DOWN;
// initial phase: legs must be switfted by 120°;
// since 360° in centered aligned is 2*MODULO,
// shift is 2*MODULO/3; in order to establish
// +120° for "leg2" and -120° for "leg3" the PHSDIR is used
/*
uint16_t per=dp_buck_period*2;
uint16_t ph_3=per/3;
switch (i) {
case 0: // leg1
case 3: // leg1
dp_buck_ch[i]->TBPHS.bit.TBPHS=0;
break;
case 1: // leg2
case 4: // leg2
dp_buck_ch[i]->TBPHS.bit.TBPHS=ph_3;
dp_buck_ch[i]->TBCTL.bit.PHSDIR = 0;
break;
case 2: // leg3
case 5: // leg3
dp_buck_ch[i]->TBPHS.bit.TBPHS=ph_3;
dp_buck_ch[i]->TBCTL.bit.PHSDIR = 1;
break;
}
*/
/*
* COUNTER/COMPARE + ACTION-QUALIFIER
*/
// CMPA/CMPB
// 50% initially
dp_inv_ch[i]->CMPA.bit.CMPA = dp_inv_period/2;
dp_inv_ch[i]->CMPB.bit.CMPB = 0;
// CMPCTL
// LOADAMODE: Load on zero (on edge zero==period)
// LOADBMODE: Load on zero (CMPB not used)
// SHDWAMODE: double buffer for CMP
// SHDWBMODE: double buffer for CMP (CMPB not used)
// LOADASYNC: shadow with ZERO/PRD
// LOADBSYNC: shadow with ZERO/PRD
// NOTE: even if buck modules are synchronized, shadow->CMP should
// happen on each module zero event, in order to ensure glitch-free
// commutation
dp_inv_ch[i]->CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD;
dp_inv_ch[i]->CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD;
dp_inv_ch[i]->CMPCTL.bit.SHDWAMODE = CC_SHADOW;
dp_inv_ch[i]->CMPCTL.bit.SHDWBMODE = CC_SHADOW;
dp_inv_ch[i]->CMPCTL.bit.LOADASYNC = 0U; // only ZERO/PRD
dp_inv_ch[i]->CMPCTL.bit.LOADBSYNC = 0U; // only ZERO/PRD
// AQCTLA
// LDAQAMODE=0 Load on Zero
// LDAQBMODE=0 Load on Zero
// SHDWAQAMODE=1 Use shadow
// SHDWAQBMODE=1 Use shadow (CMPB not used)
// LDAQASYNC=1 Use shadow for both CMP event AND sync
// LDAQBSYNC=1 Use shadow for both CMP event AND sync
dp_inv_ch[i]->AQCTL.bit.LDAQAMODE = 0;
dp_inv_ch[i]->AQCTL.bit.LDAQBMODE = 0;
dp_inv_ch[i]->AQCTL.bit.SHDWAQAMODE = 1;
dp_inv_ch[i]->AQCTL.bit.SHDWAQBMODE = 1;
dp_inv_ch[i]->AQCTL.bit.LDAQASYNC = 1;
dp_inv_ch[i]->AQCTL.bit.LDAQBSYNC = 1;
// AQCTLA
// CAU: set output when compare up
// CAD: clear output when compare down
dp_inv_ch[i]->AQCTLA.all=0U;
dp_inv_ch[i]->AQCTLA.bit.CAU = AQ_SET;
dp_inv_ch[i]->AQCTLA.bit.CAD = AQ_CLEAR;
/*
* DEADBAND GENERATOR
*/
// DBCTL
// OUT_MODE=fully enabled
// POLSEL:EPWMxB inverted
// IN_MODE=0 (source is EPWMxA)
// LOADREDMODE/LOADFEDMODE=0 (load on zero counter)
// SHDWDBREDMODE/SHDWDBFEDMODE=1 (double buffer)
// OUTSWAP=0 (no swap)
// DEDB_MODE=0 (RED on A, FED on B)
// HALFCYCLE=0 (db counters with TBCLK)
dp_inv_ch[i]->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
dp_inv_ch[i]->DBCTL.bit.POLSEL = DB_ACTV_HIC;
dp_inv_ch[i]->DBCTL.bit.IN_MODE = 0;
dp_inv_ch[i]->DBCTL.bit.LOADREDMODE = 0;
dp_inv_ch[i]->DBCTL.bit.LOADFEDMODE = 0;
dp_inv_ch[i]->DBCTL.bit.SHDWDBREDMODE = 1U;
dp_inv_ch[i]->DBCTL.bit.SHDWDBFEDMODE = 1U;
dp_inv_ch[i]->DBCTL.bit.DEDB_MODE = 0U;
dp_inv_ch[i]->DBCTL.bit.HALFCYCLE = 0U;
// DBRED/DBFED
dp_inv_ch[i]->DBRED.bit.DBRED = dp_deadtime_tick;
dp_inv_ch[i]->DBFED.bit.DBFED = dp_deadtime_tick;
/*
* TRIP ZONE
*/
EALLOW;
// TZDCSEL:
// DCAEVT1/DCBEVT1 set event when DCx is high
dp_inv_ch[i]->TZDCSEL.all = 0U;
dp_inv_ch[i]->TZDCSEL.bit.DCAEVT1 = EPWM_TZ_EVENT_DCXH_HIGH;
dp_inv_ch[i]->TZDCSEL.bit.DCBEVT1 = EPWM_TZ_EVENT_DCXH_HIGH;
// TZSEL: enable event generation for DCxEVT1
dp_inv_ch[i]->TZSEL.all = 0U;
dp_inv_ch[i]->TZSEL.bit.DCAEVT1 = TZSEL_ENABLE;
dp_inv_ch[i]->TZSEL.bit.DCBEVT1 = TZSEL_ENABLE;
// TZCTL
// TZA=2 (EWPMxA low on trip)
// TZB=2 (EWPMxB low on trip)
dp_inv_ch[i]->TZCTL.all = 0U;
dp_inv_ch[i]->TZCTL.bit.TZA = TZX_FORCE_LO;
dp_inv_ch[i]->TZCTL.bit.TZB = TZX_FORCE_LO;
EDIS;
}
EALLOW;
// FAULT_BUCK_A -> Gpio94 -> inputxbar4 -> trip4
GpioCtrlRegs.GPCINV.bit.GPIO94=1U;
InputXbarRegs.INPUT4SELECT=94U; /* inputxbar4 */
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX7=1U; // mux7/inputxbar4
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX7=1U; // enable mux7->trip4
// EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX9=1U; // mux9/inputxbar5
// EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX9=1U; // enable mux9->trip4
/* trip -> see CPU2 */
// FAULT_BUCK_B -> Gpio93 -> inputxbar5 -> trip5
// GpioCtrlRegs.GPCINV.bit.GPIO93=1U;
// InputXbarRegs.INPUT5SELECT=93U; /* inputxbar5 */
// EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX7=1U; // mux7/inputxbar4
// EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX7=1U; // enable mux7->trip5
// EPwmXbarRegs.TRIP5MUX0TO15CFG.bit.MUX9=1U; // mux9/inputxbar5
// EPwmXbarRegs.TRIP5MUXENABLE.bit.MUX9=1U; // enable mux9->trip5
EDIS;
// TRIP ZONES
// note: inputxbar/pwmxbar is configured on DSP1
EALLOW;
#if defined (HW_LOC381_0_SINGLECORE) || defined (HW_LOC381_0_DOUBLECORE) || defined (HW_LOC392_1_DOUBLECORE)
// buck A
dp_inv_ch[0]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;
dp_inv_ch[0]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN9;//EPWM_DC_TRIP_TRIPIN4;
dp_inv_ch[1]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN8;//EPWM_DC_TRIP_TRIPIN4;
dp_inv_ch[1]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;
dp_inv_ch[2]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN7;//EPWM_DC_TRIP_TRIPIN4;
dp_inv_ch[2]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;
// buck B
dp_inv_ch[3]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN5;
dp_inv_ch[3]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN7;//EPWM_DC_TRIP_TRIPIN5;
dp_inv_ch[4]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN5;
dp_inv_ch[4]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN8;//EPWM_DC_TRIP_TRIPIN5;
dp_inv_ch[5]->DCTRIPSEL.bit.DCAHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN5;
dp_inv_ch[5]->DCTRIPSEL.bit.DCBHCOMPSEL=EPWM_DC_TRIP_TRIPIN4;//EPWM_DC_TRIP_TRIPIN9;//EPWM_DC_TRIP_TRIPIN5;
#endif
EDIS;
// Adc sync on center
#if defined(HW_EVB_F28388)
EPwm7Regs.ETSEL.bit.SOCAEN = 1;
EPwm7Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
EPwm7Regs.ETPS.bit.SOCAPRD = 2; // generate SOCA on first event
EPwm7Regs.ETCLR.bit.SOCA = 1; // clear SOCA flag
#elif defined(HW_SF1220_PROTOA)
EPwm10Regs.ETSEL.bit.SOCAEN = 1;
EPwm10Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO;
EPwm10Regs.ETPS.bit.SOCAPRD = 2; // generate SOCA on first event
EPwm10Regs.ETCLR.bit.SOCA = 1; // clear SOCA flag
#elif defined (HW_LOC381_0_SINGLECORE) || defined (HW_LOC381_0_DOUBLECORE) || defined (HW_LOC392_1_DOUBLECORE)
EPwm8Regs.ETSEL.bit.SOCAEN = 1;
EPwm8Regs.ETSEL.bit.SOCASEL = ET_CTR_PRDZERO;//ET_CTR_ZERO;
EPwm8Regs.ETPS.bit.SOCAPRD = 1;//2; // generate SOCA on first event
EPwm8Regs.ETCLR.bit.SOCA = 1; // clear SOCA flag
#endif
// Enable pads and synchronize time base counters
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
/* configuration */
void DriverAdc_Config(void) {
EALLOW;
#if defined(HW_EVB_F28388) || defined(HW_SF1220_PROTOA)
/* Clock/resolution */
AdccRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcdRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
/* Set pulse positions to late */
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
/* Power up the ADC */
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
#elif defined (HW_LOC381_0_SINGLECORE) || defined (HW_LOC381_0_DOUBLECORE) || defined (HW_LOC392_1_DOUBLECORE)
/* Clock/resolution */
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdccRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcdRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCA, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCB, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCC, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
AdcSetMode(ADC_ADCD, ADC_RESOLUTION_12BIT, ADC_SIGNALMODE_SINGLE);
/* Set pulse positions at EOC. If PULSEPOS is zero, the Tint is at the end of Ts&h */
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdccRegs.ADCCTL1.bit.INTPULSEPOS = 1;
AdcdRegs.ADCCTL1.bit.INTPULSEPOS = 1;
/* Power up the ADC */
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdccRegs.ADCCTL1.bit.ADCPWDNZ = 1;
AdcdRegs.ADCCTL1.bit.ADCPWDNZ = 1;
#endif
/* Delay for 1ms to allow ADC time to power up */
DELAY_US(1000);
/* Configure SOC for ADCs */
#if defined(HW_EVB_F28388)
/* ADC C */
const int trigsel_c=0x5; /* PWM1_SOCA */
const int acq_ps=30; /* (~130ns for ADC C/D with 100ohm -> 130ns * 200MHz = 26 -> 30) */
DriverAdc_ChInit(&AdccRegs, 0, 14, acq_ps, trigsel_c); /* I_PRIM */
DriverAdc_ChInit(&AdccRegs, 1, 2, acq_ps, trigsel_c); /* I_IN_DC */
DriverAdc_ChInit(&AdccRegs, 2, 3, acq_ps, trigsel_c); /* V_IN_DC */
DriverAdc_ChInit(&AdccRegs, 3, 15, acq_ps, trigsel_c); /* TEMP */
/* ADC D */
const int trigsel_d=0xA; /* PWM3_SOCB */
DriverAdc_ChInit(&AdcdRegs, 0, 14, acq_ps, trigsel_d); /* I_PRIM */
DriverAdc_ChInit(&AdcdRegs, 1, 3, acq_ps, trigsel_d); /* V_INT1_DC */
DriverAdc_ChInit(&AdcdRegs, 2, 4, acq_ps, trigsel_d); /* V_INT2_DC */
DriverAdc_ChInit(&AdcdRegs, 3, 1, acq_ps, trigsel_d); /* AIN */
DriverAdc_ChInit(&AdcdRegs, 4, 2, acq_ps, trigsel_d); /* Iprim_DC */
/* Enable Int1 on ADC_C last SOC end of conversion */
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 3; //end of SOC3 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
/* Set handler for ADCC1 - PIE 1.3 */
PieVectTable.ADCC1_INT = &DriverAdc_ISR;
/* Enable ADCEOC in the PIE: Group 1 interrupt 3 */
PieCtrlRegs.PIEIER1.bit.INTx3 = 1;
#elif defined(HW_SF1220_PROTOA)
/* ADC C */
const int trigsel_c=0x9; /* PWM3_SOCA */
const int acq_ps=30; /* (~130ns for ADC C/D with 100ohm -> 130ns * 200MHz = 26 -> 30) */
DriverAdc_ChInit(&AdccRegs, 0, 14, acq_ps, trigsel_c); /* I_PRIM */
DriverAdc_ChInit(&AdccRegs, 1, 2, acq_ps, trigsel_c); /* I_IN_DC */
DriverAdc_ChInit(&AdccRegs, 2, 3, acq_ps, trigsel_c); /* V_IN_DC */
DriverAdc_ChInit(&AdccRegs, 3, 15, acq_ps, trigsel_c); /* TEMP */
/* ADC D */
const int trigsel_d=0x10; /* PWM6_SOCB */
DriverAdc_ChInit(&AdcdRegs, 0, 14, acq_ps, trigsel_d); /* I_PRIM */
DriverAdc_ChInit(&AdcdRegs, 1, 3, acq_ps, trigsel_d); /* V_INT1_DC */
DriverAdc_ChInit(&AdcdRegs, 2, 4, acq_ps, trigsel_d); /* V_INT2_DC */
DriverAdc_ChInit(&AdcdRegs, 3, 1, acq_ps, trigsel_d); /* AIN */
DriverAdc_ChInit(&AdcdRegs, 4, 2, acq_ps, trigsel_d); /* Iprim_DC */
/* Enable Int1 on ADC_C last SOC end of conversion */
AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 3; //end of SOC3 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
/* Set handler for ADCC1 - PIE 1.3 */
PieVectTable.ADCC1_INT = &DriverAdc_ISR;
/* Enable ADCEOC in the PIE: Group 1 interrupt 3 */
PieCtrlRegs.PIEIER1.bit.INTx3 = 1;
#elif defined (HW_LOC381_0_SINGLECORE) || defined (HW_LOC381_0_DOUBLECORE) || defined (HW_LOC392_1_DOUBLECORE)
/* Configure SOC for ADC_A -> PWMx_SOCA
* SOC0 - Ch0 - ILEGA1
* SOC0 - Ch3 - ILEGB1
* SOC0 - Ch1 - ILEGA2
* SOC0 - Ch4 - ILEGB2
* SOC0 - Ch2 - ILEGA3
* SOC0 - Ch5 - ILEGB3 */
/* With ADC running @50MHz each conversion takes 41+(acq_ps+1) SYSCLKOUT clocks
* for limits of the acq_ps register, acq_ps+1 can be up to 512 -> (41+512)/200e6=2.76us */
const int trigsel_a=0x13; /* PWM8_SOCA */
const int acq_ps_a=30; /* acq ps time for on channel (~140ns for Buck with 100ohm -> 140ns * 200MHz = 28 -> 30) (min for 12bit: 75ns = 15) */
DriverAdc_ChInit(&AdcaRegs, 0, 0, acq_ps_a-1, trigsel_a); /* I2 (inv1_leg_1) */
DriverAdc_ChInit(&AdcaRegs, 1, 1, acq_ps_a-1, trigsel_a); /* (inv1_leg_2) */
DriverAdc_ChInit(&AdcaRegs, 2, 2, acq_ps_a-1, trigsel_a); /* I3 (inv1_leg_3) */
DriverAdc_ChInit(&AdcaRegs, 3, 3, acq_ps_a-1, trigsel_a); /* (inv2_leg_1) */
DriverAdc_ChInit(&AdcaRegs, 4, 4, acq_ps_a-1, trigsel_a); /* I4 (inv2_leg_2) */
DriverAdc_ChInit(&AdcaRegs, 5, 5, acq_ps_a-1, trigsel_a); /* I7 (inv2_leg_3) */
#if defined(INVERTER_FOR_LABORATORY)
/* ADC B */
const int trigsel_b=0x13; /* PWM8_SOCA */
const int acq_ps_b=75; /* acq ps time for on channel (min for 16bit: 320ns = 65). In HW we assure that acquizition time is lower than 320ns (~260ns)*/
DriverAdc_ChInit(&AdcbRegs, 1, 2, acq_ps_b-1, trigsel_b); /* Vin */
/* ADC C */
const int trigsel_c=0x13; /* PWM8_SOCA */
const int acq_ps_c=30; /* (~130ns for ADC C with 100ohm -> 130ns * 200MHz = 26 -> 30) */
DriverAdc_ChInit(&AdccRegs, 0, 3, acq_ps_c-1, trigsel_c); /* Voltage phase U */
/* ADC D */
const int trigsel_d=0x15; /* PWM9_SOCA */
const int acq_ps_d=30; /* (~130ns for ADC D with 100ohm -> 130ns * 200MHz = 26 -> 30) */
DriverAdc_ChInit(&AdcdRegs, 0, 2, acq_ps_d, trigsel_d); /* Voltage phase V */
DriverAdc_ChInit(&AdcdRegs, 1, 3, acq_ps_d, trigsel_d); /* Voltage phase W */
#endif
/* Voltage and current need to have the same SOC in order to be on phase.*/
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 5; //end of SOC5 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared
/* Set handler for ADCA1 - PIE 1.1 */
PieVectTable.ADCA1_INT = &DriverAdc_ISR;
/* Enable ADCEOC in the PIE: Group 1 interrupt 1 */
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
#endif
EDIS;
/* enable interrupt group 1 */
IER |= M_INT1;
}
I have an EPWM running at a frequency of 9 kHz, which generates the trigger for the start of the ADC conversion. At the end of the last SOC, an interrupt is raised. I would expect the interrupt repetition frequency to be the same as the EPWM, but it is not. I observe a fixed frequency of 4.5 kHz, even when I vary the EPWM frequency itself. When sent to GPIO, the EPWM actually shows the correct frequency. The configuration codes for the ADC and EPWM are provided.
