Hello Forum Members,
I am working on implementing an NMI_ISR routine for clock fail event. In this regard, the datasheet (Piccolo System Control and Interrupts - sprufn3c) says the 16 bit NMI Watchdog Counter, NMIWDCNT, is "clocked at the SYSCLKOUT rate." (Table 28, Pg.48). I fail to understand how can NMIWDCNT be incremented at SYSCLKOUT rate (which is 60MHz in my case) , if a clock failure had caused it to increment in the first place! Or is it that the SYSCLKOUT under this circumstance would be the Limp Mode frequency, and hence NMIWDCNT would effectively be incremented at the rate of limp mode frequency.
Those of you who have handled this situation might be able to shed some light.
Thanks & Regards,
JD.
