TMS320F28P550SJ: Changing clock speed during runtime

Wayne,

Would you be able to provide more information on why user would like to reconfigure the clock in run-time. It is generally advised to configure all needed clocking configurations in the beginning and avoid re-configuration as this could have impact on peripherals and memory execution. Please see below for answers to the above questions:

Wayne Huang said:

1. Can this API be called during runtime? Any concern or usage pitfall? This changes PLL, so the user is concerned about using it.

SysCtl_setClock(DEVICE_SETCLOCK_CFG);

It is not recommended to call this during run-time as peripherals are actively using these clocks. Ensure to disable the modules, configure clocks, and re-enable modules.

Wayne Huang said:

2. Can this API be called during runtime? Any concern or usage pitfall? This does not change PLL. Is it right?

SysCtl_setPLLSysClk(uint16_t divider)

See response #1. 

Wayne Huang said:

3. After lowering clock by SYSCLK/4, if all the peripherals clocks are kept and sourced from SYSCLK. They will not be affected but the output will be changed by /4 as well.

That is,

new EPWMCLK = original EPWMCLK/4

new I2C bitrate = original I2C bitrate/4

new SCI baud rate = original SCI baud rate / 4

Is it right?

The peripherals will not automatically have the updated clock information until the registers are re-written to with the right value. If SYSCLK is updated during run-time, the peripheral execution will have issues since the peripheral registers and the SysCtrl registers will have inconsistent information. 

Wayne Huang said:

4. If the user wants to set new SCI/I2C speed = original SCI/I2C baud rate, the user has to re-initialize SCI and change the input clock in red below accordingly. 

For example,

I2C_initController(myI2C0_BASE, DEVICE_SYSCLK_FREQ, myI2C0_BITRATE, I2C_DUTYCYCLE_33);

SCI_setConfig(mySCI0_BASE, DEVICE_LSPCLK_FREQ, mySCI0_BAUDRATE, (SCI_CONFIG_WLEN_8|SCI_CONFIG_STOP_ONE|SCI_CONFIG_PAR_NONE));

Is it right?

Yes, that is correct because the old values would be currently loaded into the peripheral registers. It is recommended to reconfigure the peripherals while they are in reset / clock disabled. 

Wayne Huang said:

5. Does the user need to change flash waitstate if the user just lower SYSCLK?

It is recommended to always configure the Flash wait states as per the device freq (SYSCLK). It may be okay to keep it as is if SYSCLK is lowered, but it definitely needs to be updated when increasing SYSCLK. 

Best Regards,

Aishwarya