Tool/software:
Hello Experts,
I would like to use Core1 and Core 3 for my application. As the Shared RAM concept for F29H85x isnot same as F28x DSPs (shared message RAMs), I am unsure how to implement the Read Only message RAM from Core 3 to Core 1 and vice versa.
Could you please advise if there is a specific method?
I am currently not using any SSU.
I have been unable to locate an example of this, which is why I am asking here.
Thanking you,
Regards
Deep Ganatra