TMS320F28377D: FuSa SRAM10 example

Hi Holger,

We don't currently have a test for RAM arbitration. I've reached out to our design team for more details. They may have an internal test case that could be adapted to something that could be shared in the SDL. Will update you when I hear back.

Whitney

Hi Holger,

I've discussed with the team and can provide some suggestion. You can test arbitration by triggering repeated accesses to the same memory block from two different controllers (CPU, CLA, DMA) at the same time. You can also mix up the types of accesses by executing code from the same memory block.

For example, here's some pseudocode below showing the CPU executing code from LS0 while reading and writing to LS0 while the CLA also reads and writes to LS0.

lsramArbitrationTest()
{
    - Configure MemCfgRegs to assign MSEL and CLAPGM settings
    - Configure CLA tasks
    
    - Force CLA task so it starts executing claRWFromLS0();
    - Call cpuExecuteFromLS0()
    
    - Repeat these steps for all required LS RAMs
}

#pragma CODE_SECTION(cpuExecuteFromLS0, ".ls0ExecuteSec")
void cpuExecuteFromLS0(void)
{
	DataInitValue = 0x12345678;
	DataCheckValue = 0x12345678;

    // I'm hard-coding addresses here, but of course you can declare an array
    // and put it in LS0 if the RAM contains other things that you don't want
    // to overwrite at this point    
    DataWriteAddr = (uint32_t *)(LS0_START_ADDR + 0x450);
    DataCheckAddr = (uint32_t *)(LS0_START_ADDR + 0x450);

    // While this function executes from LS0, repeatedly write to LS0.
    // A CLA task will also be writing and reading to LS0 at the same time.
    for (i = 0; i < 200; i ++) {
        DataInitValue = DataInitValue + 0x12345678;
        *(DataWriteAddr++) = DataInitValue;
    }	

    // Read back the data that was written and make sure the writes were all
    // successful.
    for (i = 0; i < 200; i ++) {
        DataCheckValue = DataCheckValue + 0x12345678;
        if(*(DataCheckAddr++) != DataCheckValue)
        {
            ErrCount++;
        }
    }
}

// This function won't be able to be executed from LS0 since the RAM would 
// need to be set to configured as CLA program RAM to execute
#pragma CODE_SECTION(Cla1Task1, "Cla1Prog1")
__interrupt void Cla1Task1(void)
{
	ClaDataInitValue = 0x456789AB;
	ClaDataCheckValue = 0x456789AB;

    // I'm hard-coding addresses here, but of course you can declare an array
    // and put it in LS0 if the RAM contains other things that you don't want
    // to overwrite at this point    
    ClaDataWriteAddr = (long int *)(LS0_START_ADDR + 0x650);
    ClaDataCheckAddr = (long int *)(LS0_START_ADDR + 0x650);

    // Write and read back a bunch of data from LS0 while the CPU does the
    // same. Check that the accesses were successful.
    for (i = 0; i < 200; i ++) {
        ClaDataInitValue = ClaDataInitValue + 0x12345678;
        *(ClaDataWriteAddr++) = ClaDataInitValue;

        ClaDataCheckValue = ClaDataCheckValue + 0x12345678;
        if(*(ClaDataCheckAddr++) != ClaDataCheckValue)
        {
            ClaErrCount++;
        }
    }
}

You can also do a similar test between CPUs in the GS RAMs, synchronizing the start of the accesses using an IPC flag. You also need to make sure interrupts are disabled while performing these checks.

Whitney

Hi Whitney,
thanks for the answer. 

Customer is not sure about the SRAM10 requirement. What does this test (Chapter 6.5.16 in the Safety Manual) exactly mean:

"A Software Test of SRAM wrapper logic should provide diagnostic coverage for arbitration between different Masters having access to the particular SRAM and correct functioning of access protection. This is in addition To the test used to provide coverage of SRAM bit cells (See Section 6.3.12)."

What does the context mean with

• SRAM wrapper logic
• diagnostic coverage
• arbitration between various masters
• access to the particular SRAM
• access protection

Should the test test test the hardware of the TMS320 or the implementation of the software by the user? 

Regards, Holger