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TMS320F280039C: CLB out to sync EPWM internally

Wayne Huang
Genius 16705 points
Part Number: TMS320F280039C


Tool/software:

Hi champs,

I am asking this for our customer.

The user wants to use CLB output to sync EPWM.

The user can use CLB out (CLBOUTPUTXBAR) to a GPIO and then set it to EPWMSYNC by INPUTXBAR, but this method costs one GPIO.

Now, the user wonders if there is a way for the CLB output to connect to EPWMSYNC internally without costing a GPIO.

Is it possible to do so?

If yes, would you please show us explicitly?

  • 0
    TI__Expert 4320 points

    In short, there this won’t cost you GPIO. In PMP41018 reference code, the requirement to generate the synchronization event for EPWM1 module at the falling edge of EPWM1B, which can be achieved by routing FSM_S0 output to the CLB output (Output 4), and then through EPWM X-BAR to configure the synchronization scheme.

     In this design, we use two digital compare event DCA to turn OFF and DCB to turn ON the top FET of HBLLC.

    1. DCA event is mapped to T1 event which occurs due to sensed inductor current signal crossed the ramped reference current generated by outer voltage loop. On this event, we turn OFF the TOP FET. If T1 event is missed then we clamp duty to 50% by setting CMPB = PRD/2.
    2. DCB event is mapped to TRIP9 event that is coming from CLB1OUT4 connection with EPWMXBAR. This event is coming from ePWM.AQ.A FED (falling edge). On this event, we run ON TOP FET
    3. CLB1OUT4 can be connected to EPWMBAR TRIP9 as follows:
    4. Sync is generated by output lookup table 4 which is falling edge of ePWM1B event can be capture to generate the sync. Here i0 which is FSM 0 State 0 value
    5. Go to FSM0 state 0 is driven by s0, e0 and e1
    6. Boundary input is either EPWM1A AQ falling edge or EPWM1B AQ falling edge since they are same and get active high complementary (inverted) in dead-band module

    So, in nutshell, there is no EPWMSYNCIN/OUT set here for synchronization since this is variable frequency operation. Also, because of current mode control, we don’t know our ON time because T1 is generated by analog event. So, we implement logic using CLB (which involves counting till T1 event, finite state machine and lookup table) to generate this DCB event for exact 50% duty waveform.

    Regards,

    Sumit

  • +1 in reply to Sumit Patil1
    TI__Genius 16705 points

    Hi Sumit,

    This is helpful.

     

    Back to the original question, if the user just wants to use CLB output to generate an EPWM EPWMSYNCIN signal (not the sync method you showed for HHC LLC), is it possible to do so without costing the user a GPIO?

  • +1 in reply to Wayne Huang
    TI__Expert 4320 points

    Wayne,

    Yes, if you go with your proposed method then in that case you need GPIO (you can use unused GPIO especially when you are using lower/mid pin count package of the same device where many GPIO do not come to the actual pin). If you are using highest pin count then it may cost you actual pin.

    Regards,

    Sumit