[FAQ] F29x Interrupts: Frequently Asked Questions

For reference, please see F29x General FAQ for other IP/peripherals

F29x Interrupts Frequently Asked Questions

How to do I use interrupts in multi-core applications?

• Interrupts can be used in multi-core applications by utilizing the individual PIPE modules available per CPU. Refer to the F29x SDK multi-core examples for implementation details. 

When is RTINT used as an interrupt? 

• RTINTs are interrupts are maskable at the source and cannot be disabled (no global enable/disable bit for the RTINT line in the CPU). This is used for non-NMI interrupts that need to be prioritized as opposed to a normal INT. There is link based protection for all interrupts.

What is the interrupt priority set by the PRI_level field in the pipe_base.INT_config_y register? Is it correct to allocate interrupt priority from 0?

• Compared to running the high-priority periodic interrupt on CPU3, there may be additional processing requirements when running on CPU1 with AUTOSAR, depending on the interrupt category used.
• AUTOSAR - Category 1 (cat1) and Category 2 (cat2) interrupts (Section 5.1). Cat2 interrupts have higher latency compared to cat1 interrupts because of the additional overhead of OS interaction and context switching (Section 5.1) - "Cat2 ISRs have typically higher latency than cat1. This is their main advantage."
  • If the 30us high-priority periodic interrupt is implemented as a cat2 interrupt on CPU1 with AUTOSAR, there may be additional processing requirements and latency compared to running it directly on CPU3 without the AUTOSAR layer.

When running an interrupt on CPU3, are there any additional processing requirements compared to CPU1? Are there any differences? When AUTOSAR is running, will a CPU3 interrupt affect OS scheduling? Can this type of high-priority interrupt be handled in a timely manner?

• When AUTOSAR is running, this high-priority periodic interrupt can affect the OS scheduling, depending on its configuration.
  CAT2 interrupts are allowed to make most OS calls and interact with the OS scheduling (Section 5.1). If the 30us high-priority periodic interrupt is configured as a cat2 interrupt, it can preempt and affect the scheduling of other AUTOSAR tasks and lower priority interrupts (Section 6.2.2).
• Whether this type of high-priority periodic interrupt can be handled in a timely manner depends on its categorization and configuration within AUTOSAR.
  If the 30us high-priority periodic interrupt is implemented as a cat1 interrupt, it can have lower latency and be handled more timely compared to a cat2 interrupt (Section 5.1). However, the document recommends using cat1 interrupts only in limited circumstances, such as when the interrupt arrival rate is too high for cat2 overheads or when extremely low latency is required (Section 8).

After the CPU enters NMI and performs the necessary flag-clearing operations, will the CPU automatically reset if no manual reset is triggered? Under what conditions will the CPU automatically reset after entering NMI?

• After the CPU enters NMI and the ESM raw status register flags are cleared the NMIWD counter stops and resets to preload value. After this the CPU does not reset. If needed reset can be triggered manually. Also if the error flags are not cleared then the NMIWD counter expires and reset is triggered by High priority watchdog event (high priority watchdog interrupt) output.

Does entering NMI itself cause the MCU CPU to reset?

• No just entering NMI does not cause CPU to reset. The NMI WD counter in ESM has to expire to cause reset.

After entering NMI, will the CPU remain in the NMI state, or are there certain conditions under which it can return to normal operating mode?

• NMI should only occur under MCU critical error conditions. If user decides to clear error conditions and esm error flags to exit NMI isr and continue normal operation they can do so.