Tool/software:
Dear Experts,
I'm using the SPI with the FIFO enhancements enabled. I use simultaneous receive and transmit from an external source, i.e.alternating incoming and outgoing 16 bit words. The SPI is in the slave mode, receiving the SPICLK and SPIPTE signals from a peripheral. I do not use interrupts, because both the reception and transmission are synchronized to the external SPIPTE signal. I have previously succeeded in this setup when not using the FIFO buffers, so that I first read the incoming word from the SPIRFBUF and immediately then write the outgoing word to the SPITXBUF buffer, when observing the SPIPTE state. However, then I tried to utilise the FIFO, so that only every other read/write would be synchronous to the SPIPTE, and every other read/write would be handled by the FIFO. When debugging the code, I miss tx data, and correspondingly see the transmit FIFO status as 16, i.e. the buffer is immediately filled up, while the receive FIFO is ok. The transmitted data is written by two successive writes to the TXBUF, so the first is output synchronously, and assuming that the second waits for the next master PTE signal to allow it to be moved to the SPIDAT. I guess this second transfer from the FIFO and TXBUF to the SPIDAT is somehow blocked, causing the FIFO to overflow. In the documentation, chapter 22.3.3, there is a mention "...the character must be written to SPITXBUF before the beginning of the SPICLK signal" However, I assume this does not apply to the FIFO case? In the FIFO setup, the TXDLY is set to zero, which should allow back to back transfers according to the documentation. The amount of receive and transit data are strictly equal.
Please help,
Jouko
