Tool/software:
Hi Champs
I am asking this for our customer.
1.
I would like to ask whether the CPU and CLA in the F28003x device use the same clock source.
2
How can we verify that the PLL has successfully locked for both the CPU and the CLA?
3. What are the possible reasons why the PLL might still be unstable even after it has locked? For example, what if VDDIO drops to between 2.99V and 2.81V for a very short time without triggering built-in BOR. ?
Hello Wayne,
I would like to ask whether the CPU and CLA in the F28003x device use the same clock source.
Please refer to the "Clocking" section in the TRM. The CPU and CLA are both sourced from PLLSYSCLK.
How can we verify that the PLL has successfully locked for both the CPU and the CLA?
Please refer to the System Clock Setup section in the TRM and the SysCtl_setClock() function inside C2000Ware installation for an example.
What are the possible reasons why the PLL might still be unstable even after it has locked? For example, what if VDDIO drops to between 2.99V and 2.81V for a very short time without triggering built-in BOR. ?
Can you provide more details: How are they initializing the clock? What clock settings are they using? Are they using an internal or external oscillator? Are they following the PLL lock procedure in the System Clock Setup TRM chapter?
Best,
Matt
