Tool/software:
Question: There are two DSP projects, Project A (APP) and Project B (BOOT). Both projects have SPI protocol for operating the external FLASH chip. All communication codes are the same, but the CMD files are different, and the boards on which the projects run are also the same. Project A can perform read and write operations on the external FLASH chip; Project B cannot perform read and write operations on the external FLASH chip. By analyzing the SPI MOSI, MISO, and CLK waveforms using a logic analyzer, it was found that the MOSI and CLK waveforms of the two projects are the same. Project A's signal line MISO has data; Project B's signal line MISO also has data. Please analyze the cause of the error.
Self-analysis:I believe the problem lies in the non-code logical aspects of the configuration, such as linking scripts (CMD files), memory mapping, register initialization, GPIO configuration, or interrupt configuration, etc.Engineering B is the firmware upgrade code that I configured. I modified the CMD file myself.
Project A (APP)phenomenon:
The array Buffer is used for writing to the external FLASH chip array. The array BufferA reads the external FLASH chip array. As can be seen from the picture, Buffer = BufferA; In the logic analyzer, MOSI, MISO and CLK have data.
Project B (BOOT)phenomenon:
Array BufferB is used to write to the external FLASH chip array. The array BufferA reads the external FLASH chip array. As can be seen from the picture, BufferB is not equal to BufferA. In the logic analyzer, MOSI.CLK has data; MISO does not have data.
Project B (BOOT) CMD file
MEMORY
{
BEGIN : origin = 0x080000, length = 0x000002 // Update the codestart location as needed
BOOT_RSVD : origin = 0x000002, length = 0x0001AF /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x0001B1, length = 0x00024F
RAMM1 : origin = 0x000400, length = 0x000400
RAMD0 : origin = 0x00C000, length = 0x002000
RAMD1 : origin = 0x00E000, length = 0x002000
RAMD2 : origin = 0x01A000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0x8000. User should comment/uncomment based on core selection
RAMD3 : origin = 0x01C000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xA000. User should comment/uncomment based on core selection
RAMD4 : origin = 0x01E000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xC000. User should comment/uncomment based on core selection
RAMD5 : origin = 0x020000, length = 0x002000 // Can be mapped to either CPU1 or CPU2. When configured to CPU2, use the address 0xE000. User should comment/uncomment based on core selection
RAMLS0 : origin = 0x008000, length = 0x000800
RAMLS1 : origin = 0x008800, length = 0x000800
RAMLS2 : origin = 0x009000, length = 0x000800
RAMLS3 : origin = 0x009800, length = 0x000800
RAMLS4 : origin = 0x00A000, length = 0x000800
RAMLS5 : origin = 0x00A800, length = 0x000800
RAMLS6 : origin = 0x00B000, length = 0x000800
RAMLS7 : origin = 0x00B800, length = 0x000800
RAMLS8 : origin = 0x022000, length = 0x002000 // When configured as CLA program use the address 0x4000
RAMLS9 : origin = 0x024000, length = 0x002000 // When configured as CLA program use the address 0x6000
// RAMLS8_CLA : origin = 0x004000, length = 0x002000 // Use only if configured as CLA program memory
// RAMLS9_CLA : origin = 0x006000, length = 0x002000 // Use only if configured as CLA program memory
RAMGS0 : origin = 0x010000, length = 0x002000
RAMGS1 : origin = 0x012000, length = 0x002000
RAMGS2 : origin = 0x014000, length = 0x002000
RAMGS3 : origin = 0x016000, length = 0x002000
RAMGS4 : origin = 0x018000, length = 0x002000
/* Flash Banks (128 sectors each) */
FLASH_BANK0 : origin = 0x080002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK1 : origin = 0x0A0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK2 : origin = 0x0C0000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK3 : origin = 0x0E0002, length = 0x1FFFE // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
FLASH_BANK4 : origin = 0x100000, length = 0x20000 // Can be mapped to either CPU1 or CPU2. User should comment/uncomment based on core selection
CPU1TOCPU2RAM : origin = 0x03A000, length = 0x000400
CPU2TOCPU1RAM : origin = 0x03B000, length = 0x000400
CLATOCPURAM : origin = 0x001480, length = 0x000080
CPUTOCLARAM : origin = 0x001500, length = 0x000080
CLATODMARAM : origin = 0x001680, length = 0x000080
DMATOCLARAM : origin = 0x001700, length = 0x000080
CANA_MSG_RAM : origin = 0x049000, length = 0x000800
CANB_MSG_RAM : origin = 0x04B000, length = 0x000800
RESET : origin = 0x3FFFC0, length = 0x000002
}
SECTIONS
{
codestart : > BEGIN
.text : >> FLASH_BANK0, ALIGN(8)
.cinit : > FLASH_BANK0, ALIGN(8)
.switch : > FLASH_BANK0, ALIGN(8)
.reset : > RESET, TYPE = DSECT /* not used, */
.stack : > RAMM1
#if defined(__TI_EABI__)
.bss : > RAMD5
.bss:output : > RAMLS3
.init_array : > RAMM0
.const : > FLASH_BANK0, ALIGN(8)
.data : > RAMLS8
.sysmem : > RAMLS4
#else
.pinit : > RAMM0
.ebss : >> RAMLS5 | RAMLS6
.econst : > RAMLS5
.esysmem : > RAMLS5
#endif
ramgs0 : > RAMGS0, type=NOINIT
ramgs1 : > RAMGS1, type=NOINIT
ramgs2 : > RAMGS2, type=NOINIT
MSGRAM_CPU1_TO_CPU2 > CPU1TOCPU2RAM, type=NOINIT
MSGRAM_CPU2_TO_CPU1 > CPU2TOCPU1RAM, type=NOINIT
DataBufferSection : > RAMGS0, ALIGN(8)
#if defined(__TI_EABI__)
GROUP
{
.TI.ramfunc :
{ -l FAPI_F28P65x_EABI_v3.00.01.lib}
} LOAD = FLASH_BANK0,
RUN = RAMGS0,
LOAD_START(RamfuncsLoadStart),
LOAD_SIZE(RamfuncsLoadSize),
LOAD_END(RamfuncsLoadEnd),
RUN_START(RamfuncsRunStart),
RUN_SIZE(RamfuncsRunSize),
RUN_END(RamfuncsRunEnd),
ALIGN(8)
#else
GROUP
{
.TI.ramfunc :
{ -l FAPI_F28P65x_EABI_v3.00.01.lib}
} LOAD = FLASH_BANK0,
RUN = RAMGS0,
LOAD_START(_RamfuncsLoadStart),
LOAD_SIZE(_RamfuncsLoadSize),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
RUN_SIZE(_RamfuncsRunSize),
RUN_END(_RamfuncsRunEnd),
ALIGN(8)
#endif
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
Could it be that there is something wrong with the CMD file - the part with the green font that I configured myself?
