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TMS320F28388D: Data alignment issues when using shared MSGRAM

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Tool/software:

Hi TI team,

My aim is to transmit 8-bit, 16, bit, 32 bit and float data from CPU1 to CM . I used the CPU1toCMMSGRAM to do the data sharing.I can see the data assigned to the variables in struct being located at address 0x039000 for ARM core and at address 0x20080000 for the C28x core.This confirms data sharing has happened at 2 bytes word addressing in C28x and in 1 byte addressing in CM core. I try to share the data shared from the CM to my PC via Ethernet UDP communication using enet_lwip_udp.

The issue is I get extra bytes like0x00 in between, which must have been added for padding .But Im not able to see a consistency on how the padding is added across the different data.

Eg: correct data is 41 47 71 12 34 56 78 A4 70 9D 3F 00 13 00 08 07 E9 3B D8 C6

But I receive: 41 | 00 | 47 | 71 | 00 | 03 | 00 | 78 | 56 | 34 | 12 | A4 | 70 | 9D | 3F | 13 | 00 | 08 | 00.

    gSharedSettings.handshake.sourceID  = 0x41;
    gSharedSettings.handshake.destID    = 0x47;
    gSharedSettings.handshake.hndcmd    = 0x71;
    gSharedSettings.handshake.Checksum = 0x12345678;
    gSharedSettings.handshake.Version  = 1.23f;

    gSharedSettings.handshake.day   = 0x0013;
    gSharedSettings.handshake.month = 0x0008;
    gSharedSettings.handshake.year  = 0x07E9;
    gSharedSettings.handshake.ready = 1;
The data types are: 
typedef struct {
       uint8_t  sourceID;     // e.g., 0x41 (CPU1)
       uint8_t  destID;       // e.g., 0x47 (CPU2)
       uint8_t  hndcmd;       // cmd
       uint32_t Checksum;   // 4-byte checksum
       float    Version;    // IEEE-754 float (e.g., 1.23f)
       uint16_t day;          // DD
       uint16_t month;        // MM
       uint16_t year;         // YYYY
       uint16_t ready; 
} HandshakeSettings;
I assume the mismatch between actual data and data received happened because of the memory alignment difference between C28x and CM.But how to correct it? I tried #pragma PACK(1).

  • Hi Sapna,

    Do you happen to be using the IPC_sendCommand? If so, are you using the addrCorrEnable functionality, this while handle the addressing difference between both cores. 

    Kind regards,
    AJ Favela 

  • Hi,

     I have not used the IPC or  IPC_sendCommand yet. Is IPC interrupt based? I am not familiar with IPC.To make things simple , I used the shared MSGRAM between CPU1 and CM. I tried various options in the existing code. But not able to resolve. 

  • Hi,

    Yes IPC is interrupt based, but can also work by continuously checking IPC flags. IPC also uses the MSGRAM between CPU1 and CM when using the IPC_sendCommand.

    There are already working examples of IPC communication between CPU1 and CM that can be found in C2000Ware at the location C2000Ware_VERSION#/driverlib/DEVICE_GPN/examples/CORE_IF_MULTICORE/ipc. 

    Additionally I would recommend going through the IPC chapter of C28x academy to better understand how this peripheral works 

    Kind regards,
    AJ Favela