• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 82 subscribers
  • Views 134 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28P650DK: How to use Trip signal to build a long lasting signal as CLB input

Joe Ji
Expert 3980 points
Part Number: TMS320F28P650DK


Tool/software:

Hi Expert

This thread is the following up thread for: TMS320F28P650DK: Need to generate 2 us delay once PWM TZ happens in OC fault situation.

I will use the below method to recreate a PWM output:

But I find that the protection signal (GPIO11/Tz) is a pulse, so with the logic expression I0&I1+~I0&I2 the output will always, cannot change to I2 even the trip happens.

Is there any method to get a long lasting signal to indicate the TZ happens so the I2 can be switched to output?

Thanks

Joe

  • 0
    TI__Mastermind 28220 points

    Hi Joe,

    I will get back to you on this question on Tuesday 9/2 since it is a U.S. holiday tomorrow, apologies for the delayed response.

    Thank you,

    Luke

  • +1 in reply to Luke Jones
    TI__Mastermind 28220 points

    Hi Joe,

    If you want a trip signal to persist in your CLB logic, you could use a finite state machine whose state changes from a 0 to a 1 when a trip signal occurs. If you need to clear this trip signal you could use a software GPREG input to clear the FSM state from a 1 to a 0. Let me know if you need assistance with this implementation.

    Thank you,

    Luke