TMS320F280037C: Mcan module, can speed setting

Hello Joseph,

Thank you very much for your clarification. In my last question i was refering to the following: 

- In order to two nodes to coexist in the same network need to be configured to the same speeds. However, there are many combinations regarding the different time quanta settings and CAN controller clock that mainly affect to the sample point and synchronization jump width. These parameters can differ between nodes? How much can they differ?

Regards,

David

Hello again Joseph,

I have another question regarding the MCAN. Which behavior should be expected by using parameters outside specifications, for example, If i where to choose a data bit rate of 6MHz, should i be able to see some kind of message though the can line eventhough they might be corrupted or the MCAN module prevents from working if detecting a speed outside its specified range? Is there any possibility to work outside specifications at our own risk?

Hi David,

Yes, Tseg and SJW can vary between nodes to satisfy the sampling point.  This all really depends on bus length interconnect and propagation delays between nodes.  You can definitely try higher data baud rates for MCAN.  I think MCAN will work at 6Mbps but you would probably need to enable transmitter delay compensation (TDC) on the F28003x MCAN if these nodes were to transmit MCAN frames to compensate for transmission prop delay.  Reason is that, during MCAN frame transmission, the transmitted data is automatically sampled on the RX pin on the F28003x.  If there is a propagation delay, or if the baud rate is over 3Mbps, the delay becomes significant with respect to the bit time, hence a propagation delay compensation is required to satisfy the sampling requirement.

Regards,

Joseph

Hello Joseph,

Thank you for your help. We might be able to settle with 6Mbps and it is for sure a good start, we will try different endurance testing just to make sure the network is still robust and we would like to see the module maximum capabilities. Also, we would like to try out an arbitration speed of 2MHz as all nodes in our network are canFD compatible. Let me add 3 more questions.

- How much do you think the can speed can be pushed for both speeds? I understand we are doing it at our risk. I am asking this because the current MCU we are using only allows a minimum prescaler of 2 in MCAN clock. This means that having a sysClk of 120MHz there is now way possible have an 80MHz clk with this f280037C right? This decision is quite important as we need to decide if maintain this mcu for a new project or search for another one with higher clock speed just to be able to use the 80MHz. But before that, we are worried to not be able to push further can speed.

- Another thing we are quite worried is that whether there is there any requirement regarding its speed compared to the SysClk. Does the system need to be working to a much higher frequency to properly communicate with mcan module? Or could it be working independtly?

- Finally we did some quick testing by adjusting the MCAN speed to 60MHz and using a data bit rate of 6MHz and 1MHz of arbitration, the results can be seen in the message reception pcan software. It seems the MCAN module enter in error because of the transmission errors. Could it be caused because of what you mentioned of the delay compensation(I attach the pcan software message reception, these are error in Rx meaning that the transmitter is the one throwing errors)? Can you please explain me how to properly adjust the delay compensation? How can obtain the requirements of offset and filter window length?

Thank you for your help,

David

Hello David,

Maximum bit rate attainable for CAN would largely depend on your system implementation.  Shorter bus lengths would allow you to realize higher bit rate but good to experiment for sure.

Yes, a bit tricky to get 80MHz MCAN clk from SYSCLK.  You drop SYSCLK to 80MHz and use a div by 1 for MCAN but that means other modules and CPU will be executing at slower clock of 80MHz.  One option that I have not tried, but would probably work is to source MCAN CLK from PLLRAW CLK.  In the clocking diagram of F28003x below, PLLRAW clock is the output clock of the PLL:

Diving PLLRAWCLK with SYSCLK divider will produce SYSCLK.  So if PLLRAWCLK is configured to 240MHz and PLLSYSCLKDIV = 1 (divide by 2), the SYSCLK is 120MHz.  In the MCAN block, the MCAN Bit Clock can be derived from AUXCL (60MHz max) or SYSCLK (120MHz max) or PLLRAW Clock (240Mhz max).  You can then set the MCAN clock divider to 3 to produce the 80MHz MCAN clock.  You'll have more granularity with tq with 80MHz MCAN CLK.

I think the other two questions are answered from the above.  As for the last question on transmission errors, no TDC (tx delay compensation) typically produces bit errors if this is an issue.  You can check the contents of MCAN_PSR register (LEC) for the reported error.  No TDC is likely the cause of the TX errors..

Regards,

Joseph