Tool/software:
Hi,
As I understand, when the ECC test mode is enabled, the CPU no longer fetches data from Flash. Instead, it retrieves data from the ECC test mode registers.
In this scenario, what would happen if an interrupt is triggered and its ISR (interrupt service routine) is located in Flash? My assumption is that in such a case, the ISR would not be executed successfully.
To handle this, I see two possible approaches:
-
Disable interrupts before enabling ECC test mode if the ISR resides in Flash.
-
Place all ISRs in RAM so that they can still be executed during ECC test mode.
Could you please confirm whether my understanding is correct, and what is the recommended practice in this situation?
Thank you.
Best Regards,
Norman
