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TMS320F28377D-EP: SW Triggered ADC Interrupts stop

Keyur Kulkarni
Prodigy 10 points
Part Number: TMS320F28377D-EP

Tool/software:

Hello,

I am using TMS320F28377D-EP in my product.
In my Firmware, the ADC gets SOC from 2 sources: one is via EPWM module (PWM-synced Interrupts) and another is SW-triggered SOC (Force SOC operation). These are spread accross all the ADC modules (A, B, C, D).

The PWM triggered SOCs happen once every 50us and their ISRs last for approx 3us.
I am triggering different SOC via SW every 300ms sequentially (I don't trigger the next SOC until ISR of previous SOC is done). ISR function corresponding to the SOC gets executed. However, after certain time, I don't receive the ISR of the triggered SOC (it is not a specific SOC but any one from my sequence) and my sequence remains stuck (which means I am almost never getting the ISR of that SOC). The PWM-triggered ISRs (even those from the same module) don't stop here.

From the Errata (link / Page 12 / Interrupts may Stop if INTxCONT (Continue-to-Interrupt Mode) is not Set), I understand that this might be happening when I am asserting INTGLFCLR when some other interrupt is asserting INTFLG.

Is my above understanding correct?

I feel that the condition described in Errata, if arising for SW triggered ISRs, then it could happen for PWM-synced ISRs also. However, I haven't observed this error for PWM-synced ISRs at all.
Does the condition mentioned in Errata apply to only SW-triggered interrupts and not PWM-synced ones or is it applicable for all ADC interrupts?

  • 0
    TI__Expert 4200 points

    Hello,

    It is not common to use two trigger sources for ADC SOC because it can induce these issues. Is there specific reason why you need to use both triggers?

  • 0 in reply to Stevan Duraskovic
    Prodigy 10 points

     ,

    Thanks for response,

    My application requires Analog sensing to be triggered at a specific time of PWM signal; hence the PWM-triggered ADC.
    The other Analog channels are not as critical as above, so they are being triggered via the Firmware (by Force SOC operation); hence the SW-Triggered ADC.
    (I hope this answers what u were asking)

    I stumbled upon the limitation of the microcontroller while I was debugging SW triggers (not before, else would have tried to avoid).

    I am having a similar observation as described in the article from Errata document I quoted above, viz., after I retry Force SOC operation (after getting stuck with no ISR), everything works fine (I am able to receive ISR and everything).
    The intent of me asking this is, that, with the retry is there a possibility that this will get stuck again? Also, are the PWM-synced ISRs immune to this and have a better reliability (in this case)?

  • 0 in reply to Keyur Kulkarni
    TI__Expert 4200 points

    Hello Keyur,

    To work around the issue:

    1. Use Continue-to-Interrupt Mode to prevent the ADCINTFLG from blocking additional ADC interrupts: ADCINTSEL1N2[INT1CONT] = 1; ADCINTSEL1N2[INT2CONT] = 1; ADCINTSEL3N4[INT3CONT] = 1; ADCINTSEL3N4[INT4CONT] = 1;

    2. Ensure there is always sufficient time to service the ADC ISR and clear the ADCINTFLG before the next ADC interrupt occurs to avoid this condition.

    3. Check for an overflow condition in the ISR when clearing the ADCINTFLG. Check ADCINTOVF immediately after writing to ADCINTFLGCLR; if it is set, then write ADCINTFLGCLR a second time to ensure the ADCINTFLG is cleared. The ADCINTOVF register will be set, indicating an ADC conversion interrupt was lost

    Please let me know if this helps.

  • 0 in reply to Stevan Duraskovic
    Prodigy 10 points

     ,

    Hi,

    The 3rd point can be helpful, thanks. I also had discovered this method while debugging this issue.

    However, I wish to know if this same behavior is recreatable for PWM-triggered ADC signals. In my limited work with the controller, I haven't observed yet, but can you confirm this?

  • 0 in reply to Keyur Kulkarni
    TI__Expert 4200 points

    Hello,

    The condition described in the F28377D errata ( “Interrupts may stop if INTxCONT is not set” ) is not limited to software‑forced SOCs – it applies to any ADC interrupt, whether the conversion was started by an ePWM‑triggered SOC or by a Force‑SOC command. If the continue‑to‑interrupt bit (INTxCONT) is cleared and the ADC interrupt flag (ADCINTFLG) is still asserted when you write to the global‑clear register (INTGLFCLR), the flag can become “latched” and subsequent ADC interrupts are blocked until the flag is cleared again. The same thing can happen with PWM‑triggered conversions; you just haven’t hit the timing corner yet.