Other Parts Discussed in Thread: TIDM-1010
Tool/software:
I'm trying to reconcile the CLB diagram generated by the PM_vissc_f28965_lib (PM_bissc_f28p65x_lib\RELEASE\diagrams\clb.svg) and Figure 2-10 of Design Guide: TIDM-1010
BiSS-C Absolute Encoder, Master-Interface Reference Design for C2000
MCUs (TIDUE73A – APRIL 2018 – REVISED NOVEMBER 2024). Figure 2-10 (pg14) indicates that Tile 3 OUTLUT1 connects to Tile 4 In2 and In3 and that Tile 3 OUTLUT2 connects to Tile 4 in4 and in5 but the generated diagram has tileOutput_TILE3_2 connected to boundaryInput2 and boundaryInput3 and tileOutput_TILE3_1 connected to boundaryInput4 and boundaryInput5 - they are reversed.
Also, the User's Guide CLB Tool (SPRUIR8B – APRIL 2020 – REVISED JULY 2023) in section 3.3 indicates that "Boundary" are for simulation only - it states this repeatedly, simulation only.
I have three questions:
1) Which diagram is correct? The one generated when the library is built or the design document? Does this example actually work given the discrepancy? if so, what else is wrong with the documentation?
2) How do you specify which outputs correspond to the OUTLUTs? Figure 2-10 indicates, for example, that Tile 4 OUTLUT5 uses out21, how is out21 associated with OUTLUT5?
3) Are the TILEx_BOUNDARY designations in the generated diagram the actual tile inputs or are they simulation only as the tool guide emphatically indicates?
I should note that I am trying to get this example to run on the F28388D and therefore I need to make changes to the various connections, e.g., I must use SPI-A which means I must change put Tile 4 on CLB 1 (the nomenclature change of Tile to CLB is also disconcerting), and I need to change GPIO pins. In order to effect the port I need to understand and trust the various documents and diagrams.
