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TMS320F28P650DK: CANBUS Flash Kernel Inquiries

Ayden Bourdeau
Prodigy 100 points
Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Tool/software:

Hi,

I am currently working on trying to get the CAN flash kernel working for remote firmware updates using the P65x. I have successfully followed all of the steps in the CAN Flash Programming for C2000 Microcontrollers but unfortunately am unable to get the flash kernel working. I had a couple of points that I was unsure about during the process I want to clarify.

1. I used the sample dcan_flash_kernel_c28x_dual_ex5 project and modified the following line to my configuration inside of the flash kernel main

    return DCAN_Boot(CAN_BOOT_ALT3, 0, 1, 25, 5, Application_Flash_Banks,
                     WE_Protection_A_Masks, WE_Protection_B_Masks, WE_Protection_OTP_Masks);
CAN_BOOT_ALT3 moves the CAN pins on the kernel to GPIO36 + GPIO37 which is what I use on my custom board. Please note I also have a 25MHz XTAL
In this Kernel setup, do the OTP regs need to be programmed on the device to also have this running? Inside of the P65x TRM, table 4-49 mentioned that a value of 0x62 should be programmed into the BOOT_DEF memory at Z1-OPT-BOOTDEF-LOW + Z2-OPT-BOOTDEF-HIGH. I did not program these as I want to verify that the kernel is running. Do I need to program these alongside building the kernel?
2. I remained on the default BOOT pins (GPIO84 + GPIO72) for getting this working. I currently have a toggle switch i am manually switching to get to and from FLASH + CAN Boot modes. Just confirming this is valid. I will eventually be changing to a setup similar found in SPRACN1 " C2000 Software Controlled Firmware Update" so this will be automatic.
3. I have confirmed my CAN line is good, I am not using the PEAK PCAN-USB Pro FD CAN bus Analyzer but am using the regular PCAN-USB. I assumed the API's are universal on PCAN so the kernel should still work? Not sure if this is valid or not.
I am able to program following the instruction in the CAN Flash Programming Guide where it tells me in verbose mode that the Kernel is loaded + Application is loaded for some sample blinky projects I made. However after resetting the device and moving back to flash boot my old program still remains in flash, meaning the kernel never gets loaded into RAM to clear FLASH banks 1-5.
Any information surrounding any of these questions would be appreciated!
  • 0
    TI__Guru**** 198746 points

    Hi Ayden,

    There are on DCAN module and two MCAN (CAN-FD) modules on F28P65x device.  GPIO36 and GPIO37 are mapped to both DCANA and MCANA RX/TX. Which CAN are you using?

  • 0 in reply to QJ Wang
    Prodigy 100 points

    It was my intention to use the DCAN, as the ROM bootloader section of the TRM indicates you have to use module A of each communication port in order to perform firmware updates. The CAN boot table on page 297 of the P65 datasheet indicates that only GPIO36 + GPIO37 are module A of the DCAN (as option 4).

    Thanks

  • 0
    TI__Guru**** 198746 points
    Ayden Bourdeau said:
    I remained on the default BOOT pins (GPIO84 + GPIO72) for getting this working.

    GPIO84 and GPIO72 are used to select the ROM bootmode: SCI, CAN, or Flash, etc. 

    About which pins are used for CAN boot, please program the "EMU-BOOTDEF-LOW" 0x0D04. Please refer to table 4-17 of device TRM, and the app note "sprad51a_CAN_Flash_Programming.pdf"

    6. In emulation mode, the following memory locations need to be set to enable CAN boot mode: a. Location 0xD00 with 0xFFFF b. Location 0xD01 with 0x5AFF c. Location 0xD04 with 0x00XX where XX is the boot mode for CAN Boot – 0x02, 0x22, 0x42 or 0x62. The SENDTEST CAN Boot modes of 0x82, 0xA2, 0xC2 and 0xE2 use the same pins as the first four configurations, respectively, and they also send out two CAN frames. In evaluation mode, using one of the SENDTEST modes ensures that the CAN module does not time out before the host starts sending the flash kernel over. To learn more about the SENDTEST modes, consult the DCAN boot source file located in C2000Ware (C2000Ware_x_xx_xx_xx > driverlib > f28003x > examples > flash > DCAN_Boot.c).

  • 0 in reply to QJ Wang
    Prodigy 100 points

    Just confirming i am writing to this ROM and performing a reset correctly.

    I have written to these addresses before as discussed in the CAN Flash Programming document. A couple of follow up questions.

    1. In the dcan_flash_kernel_c28x_dual_ex5 sample project for P65x are there modifications I need to make to the program or do these temporary OTP emulations cover everything I need to configure to get a base flash programmer running? 

    2. I notice that the dcan_flash_programmer executable in verbose mode will tell me kernel + application loaded regardless if I have a device connected on the other end of the bus or not, I take it the communication is in auto acknowledge, is there a way to test using another utility if the programmer can actually see my device?

    3. Inside of the project, I put a breakpoint directly after this statement

        //
        // Wait for a new CAN message to be received in mailbox 1
        //
        while((HWREG_BP(CANA_BASE + CAN_O_NDAT_21) & CAN_MSG_OBJ_1) != CAN_MSG_OBJ_1)
            {
            }
     
    But even validating some of the messages with a logic analyzer this while loop is never exited. I was wondering if there was something I am missing in the configuration to setting up these pins for DCAN (as you said GPIO 36 + GPIO 37 can be used for MCAN + DCAN).
    Thanks again for your help
  • 0 in reply to Ayden Bourdeau
    TI__Guru**** 198746 points

    I will double check if the mode supports the DCAN pins used in your application. Will come back to you afternoon.

  • 0 in reply to Ayden Bourdeau
    Prodigy 100 points

    Just a follow-up after investigating a bit more.

    I have programmed the EMU_BOOTDEF_LOW (0xD04) to move the GPIO Configuration to GPIO36 + GPIO37. I have investigated a bit and noticed that my current hardware doesn't match the bit timing for the current Kernel. I am manually changing the GPIO toggle pins so I left D00 and D01 alone.

    I have the following I am passing into DCAN_BOOT inside the call to the kernel

    CAN_BOOT_ALT3 -> as the bootmode

    bitTimingRegValue = 0x7FC0 (math i obtained with 1Mbps with a 25Mhz XTAL and BITTIME = 25). The CALC_CANCLK according to the TRM is the value of the unprescaled CAN clock which I am assuming is XTAL (when i add a sysconfig the clocktree doesn't show up for me to double check as an option so this is an assumption).

    I had one follow up question to my previous taken from sectioin 4.1.2 Point 2 of Application load CAN Flash Programming of C2000

    2. The flash kernel is transferred to the device with 2 bytes of data per frame. The host programmer will transmit frames to the device, checking if data bytes 3 and 4 are non-zero values. Bytes 3 and 4 of the text file must be replaced with the hex value calculated from the final result of the bit timing register value (CAN_CALC_BTRREG) in order of least significant byte followed by the most significant byte. If the host programmer recognizes a bit-timing change with bytes 3 and 4, the host programmer will then send the bit-timing change to the device and re-initialize itself (skipping the following 7 reserved words). The device will increase the bitrate to the desired bit-timing and continue to receive frames until the kernel has finished download.

    Can you confirm this is the only bytes I need to change inside of my generated kernel file? This is to match the CAN_BTR reg.

    Thanks again 

  • 0 in reply to Ayden Bourdeau
    TI__Guru**** 198746 points
    Ayden Bourdeau said:
    I am manually changing the GPIO toggle pins so I left D00 and D01 alone.

    The EMU-BOOTPIN-CONFIG is used to select the boot pins. It is located at 0xD00. It's upper byte [31:24] must be 0x5A, and the bit[7:0] (BMSP0) and bit[15:8] (BMSP1)  set the GPIOs to be used during boot. For you case, the BMSP0 is 36 (GPIO36), and BMSP1 is 37 (GPIO37).

    The value at address 0xD04 is to define the boot mode and boot options. For CAN boot, the bit[3:0] is 0x2.

    Ayden Bourdeau said:
    Can you confirm this is the only bytes I need to change inside of my generated kernel file? This is to match the CAN_BTR reg.

    The CAN clock in the kernel may not be the crystal clock. It may be 20MHz or 25MHz which is defined in ex_5_bootloader_can_timing.h. Please check the example you used.

    BYTE3=0xC0 --> SJW=3, and BRP=0;

    BYTE4=0x7F -->TSEG1=15, and TSEG2=7.

    If the CAN clock is 25MHz, the baudrate will be 25MHz/(25) = 1mbps