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TMS320F280025C-Q1: CMPSS DAC: consideration to assess max error when used as windows comparator?

AnBer
Mastermind 31375 points

Part Number: TMS320F280025C-Q1

Tool/software:

Team,
Could you please help with the below:

We use COMP and DAC elements to create a window comparator.

COMPH and COMPL are coupled with OR logic to trigger an interrupt when passing through the window.

The two window thresholds are determined from two DAC outputs.

The DACs are powered by VDDA (3.5V).

The two thresholds are close together, raising the question of error distribution, which could, in the worst case scenario, lead to a reversal/overlap of the two thresholds.

Our current configuration:


Hysteresis x4
DAC H VAL (1931-80)LSB
DAC L VAL (1931+128)LSB

Question 1
In the datasheet SPRS45 section 6.12.5.1.3 CMPSS illustrative Graphs:
Is it possible, based on these curves, to evaluate the error around our operating point (1931 LSB) rather than taking the maximum error and applying it to the entire DAC range (worst-case method)?

Question2:
Is it possible to consider a strong error dependency between the two COMPH/COMPL elements?
Is it possible to consider a strong error dependency between the two DAC elements?
In which case, the two thresholds will vary in the same direction and will not risk inversion/overlap of the two.

Thanks in advance,

Anthony

  • 0
    TI__Expert 7910 points

    Hello,

    I will take a look and reply in next couple of days.

  • 0 in reply to Stevan Duraskovic
    TI__Guru* 86240 points

    I'm replying here to keep the post up to date.  I'm looking to see if we have some characterization or simulation data that might help give some direction here.  

    Best,

    Matthew

  • 0 in reply to MatthewPate
    TI__Guru* 86240 points

    Anthony,

    Here is feedback we can share with the customer: 

    The DAC used inside a CMPSS is common to both low and high Comparators(it is a dual tap DAC), so gain error will be identical inside a CMPSS module and cancel out.

    The factors then to consider for min separation would then be INL and Comp Offset

    Max difference would be(for DAC reference of VDDA = 3.3V) INL + sqrt(2) * comp offset = 32LSB + 1.41 * 25LSB = 67LSB

    The other parameter to consider is shown in the below highlight from the DS:

    When one of the COMP trips it will introduce a momentary glitch on the other DAC, but customer can account for this with digital filter block in the CMPSS if needed. 

    Since customer is using this to window on same input, this may not matter at all though, since if there is a break in the upper or lower threshold of the CMPSS, we will trip and perhaps the output of the other CMPSS is a don't care during this time.

    Best,

    Matthew