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F29H85X-SOM-EVM: Use of different peripheral Frame for different Cores

Deep Ganatra
Prodigy 161 points

Part Number: F29H85X-SOM-EVM
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hello experts,

I am wondering if, for peripheral sharing between CPU Cores, there is a strict rule to use different frames for access? And if these frames are defined without use of any SSU?

I am working on multicore setup, but right now I don't want to use any SSU. Can I then just use same frame? Or do I need to use different frames for different CPU cores?

Is there anything wrong with the defined peripheral initialisation code below?

Thanking you in advance

Regards 
Deep Ganatra

  • 0
    TI__Mastermind 20505 points

    Hi Deep,

    The SSU is independent of the peripheral frames concept, so there is no requirement to use it. 

    It is fine to access all peripherals within the same frame but note the arbitration scheme listed in the TRM (3.6.2 Peripheral Access Configuration using FRAMESEL, 3.6.3 Bus Arbitration)

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    Prodigy 161 points

    Thank you Aishwarya for the reply. 

    Do you have a working example for the same? I am not sure why is this not working in my case. 

    Thanking you

    Regards 
    Deep

  • +1
    TI__Mastermind 20505 points

    Deep,

    It is fine to use FRAME0 for all accesses across CPUs, but for faster accesses without arbitration stalls between CPUs, you should have the different frames configured. Utilize SysConfig for peripheral initialization, which generates the frame configurations in device.c + peripheral_frame_mapping.h (likely the file you are missing). You can refer to any example for these details.

    Best Regards,

    Aishwarya

  • 0 in reply to Aishwarya Rajesh
    Prodigy 161 points

    Thanks Aishwarya for the reply. 

    I have a doubt regarding that code generated peripheral_frame_mapping.h file, 

    Does the mapping of xlink also needs to be done? 

    Like this? (as I am not plaing around with SSU or any xlink right now)

        #define ECAP3_BASE                                      ECAP3_BASE_FRAME(1)
        #define ECAP4_BASE                                      ECAP3_BASE_FRAME(1)
        #define EPWM16_BASE                                  EPWM16_BASE_FRAME(0)
        #define EPWM16XCMP_BASE                        EPWM16XCMP_BASE_FRAME(1)
        #define EPWM16DE_BASE                             EPWM16DE_BASE_FRAME(1)
        #define EPWM16MINDBLUT_BASE                EPWM16MINDBLUT_BASE_FRAME(1)
        #define EPWM16XLINK_BASE                      EPWM16XLINK_BASE_FRAME(1)
        #define EPWM16XCMPXLINK_BASE            EPWM16XCMPXLINK_BASE_FRAME(1)
        #define EPWM16DEXLINK_BASE                  EPWM16DEXLINK_BASE_FRAME(1)
        #define EPWM16MINDBLUTXLINK_BASE    EPWM16MINDBLUTXLINK_BASE_FRAME(1)


    Thanking you in advance. 

    Regards 
    Deep

  • 0 in reply to Deep Ganatra
    Prodigy 161 points

    One more thing, 

    Now I could update these address as u can see for CPU1 on left and CPU3 on right, But the CpuTimer1Regs for both the CPU has same address, is this normal? 

    I read both the CPUs have 3 timers and thus it should have different address, right? Maybe I am doing something here wrong, thus asking. If I do also have to initialize such address for other timers. 

    Regards 
    Deep





  • 0
    TI__Mastermind 20505 points

    Deep,

    Deep Ganatra said:
    Does the mapping of xlink also needs to be done? 
    Aishwarya Rajesh said:
    Utilize SysConfig for peripheral initialization, which generates the frame configurations in device.c + peripheral_frame_mapping.h (likely the file you are missing). You can refer to any example for these details.

    Yes, this is needed for all peripherals, and it looks like you may have referred to the SysConfig generated code for implementation details. 

    Deep Ganatra said:

    Now I could update these address as u can see for CPU1 on left and CPU3 on right, But the CpuTimer1Regs for both the CPU has same address, is this normal? 

    The CPU Timers are not frame applicable which is why you see different base addresses in the map file as mentioned here in the TRM and datasheet.

    Best Regards,

    Aishwarya