Other Parts Discussed in Thread: TMS320F28388D
Tool/software:
Hello,
I'm working on adding CAN FD support to our bootloader. The customers of the bootloader will be able to pick a baud rate and data rate and the build system should then pick sufficient parameters that satisfy that requirements. Basically, I put the logic from TI excel sheet into a script that runs as part of the build.
That works fine, as long as I do not use Bit Rate Switching. When I for example use a CAN clock of 200Mhz, the peripheral works without Bit Rate Switching, but not with BRS (the transmitted bit pattern is way too short and wrong).
Now, I've stumbled of a requirement for the TMS320F28388D, that according to this post: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1527758/tms320f28388d-rationale-behind-setting-mcanclkdivsel-to-3-in-the-mcan-external-loopback-example-for-m4?tisearch=e2e-sitesearch&keymatch=MCAN%205M%20P65# there is a limit that MCAN_FCLK has to be between 20Mhz and 80MHz.
Question1: Does the same limit apply to the F28P65x?
Question2: If so, is that documented somewhere? (Have't found any, neither in the Reference Manuel, nor in the Data Sheet, neither in the documentation of MCANxCLKDIV, nor in the documentation of the peripheral itself)
best regards
Torsten
