Other Parts Discussed in Thread: C2000WARE
Tool/software:
Content:
In our system, we are currently using XTAL as the system clock source.
I am configuring the DCC with INTOSC2 as Clock0 (reference) and PLLRAWCLK as Clock1 (test) to ensure the PLL output is operating correctly.
However, I am concerned about the scenario where the XTAL fails (open/stop). In that case, the PLL will lose its input source, which may cause the CPU to lose its system clock and potentially freeze. This would prevent the DCC error from being detected and handled.
From my understanding, when the MCD detects a missing clock, it will automatically force the PLL to bypass and switch the clock source to INTOSC1, allowing the CPU to continue running at a fallback frequency. I did not find a similar mechanism described in the DCC section.
Therefore, I would like to clarify the following:
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If DCC is configured with INTOSC2 (Clock0) and PLLRAWCLK (Clock1), and the XTAL fails:
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Will this immediately cause the CPU to freeze, so that the XTAL failure cannot be diagnosed and the SYS_ERR interrupt cannot be triggered?
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Or will the system still be able to run for some time?
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If the CPU does not freeze and the system continues running for some time:
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My plan would be to switch the system clock source to INTOSC1 or INTOSC2 inside the SYS_ERR ISR to maintain basic operation.
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How can I ensure that the SYS_ERR ISR is reliably executed in this case? Does it mean I need to guarantee handling within a certain systick period?
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If the CPU will freeze when XTAL fails:
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Does it mean that I must use both MCD and DCC together?
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With MCD responsible for detecting a missing clock and automatically switching the source to INTOSC1 to keep the CPU alive,
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While DCC is used primarily to check the clock frequency tolerance.
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Thank you very much for your support and clarification!
