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F29-SDK: F29 Flash/UART Booting Inquiry

Cesc Yang
Intellectual 261 points

Part Number: F29-SDK

Tool/software:

Hi TI,

We had a meeting with a potential customer for the F29 today. They have an request regarding their F29 mass production. They are using locked flash boot mode for production, therefore need to be able to program the device in this state without switching to UART boot mode.

Based on our current experience and understanding, the official F29 programming method involves booting from UART, then using the uart_flash_programmer PC tool to load and run the flash kernel binary. From there, the uart_flash_programmer interacts with the flash kernel running in RAM to transfer other images for programming.

To address the customer's need, we believe two things are required:

  1. A version of the flash kernel project or binary that can be flashed onto the F29 and will boot from flash.

  2. The uart_flash_programmer must be able to properly communicate and interact with the flash kernel when it is started from flash boot mode.

Can you confirm if our understanding is correct? Will there be updates or solutions available from TI to meet this customer requirement?

  • +1
    TI__Expert 6545 points

    Hi Cesc,

    There is a flash-based project in the SDK that supports this (f29h85x_sdk_installation\examples\driverlib\single_core\flash\flash_based_sbl_with_fota). This example can be used for FOTA or for flash-based bootloading. Please take a look at the SDK documentation (29h85x_sdk_installation/docs/html/EXAMPLES_DRIVERS_FLASH_BASED_UART_SBL_WITH_FOTA.html) for more information. 

    Kind regards,

    Skyler

  • 0 in reply to Skyler Baumer
    Intellectual 261 points

    Hi Skyler,

    Thanks for the prompt reply! However, I'm having trouble flashing the image on HSSE devices. Please refer to the image below.

    Also I find the device's flash not being able to erase. If I try to erase the flash on CPU1, the CCS will report:

    What's causing this? Is this expected?

    Best Regards,

    Cesc

  • 0 in reply to Cesc Yang
    TI__Genius 15080 points

    Hi Cesc,

    Is the device in Bank Mode 1 prior to programming the example?

    Is the generated .out from the repo? If not, can you send your .out file that you are loading to the device for testing? I've sent a friend request to you.  

    Thanks and regards,

    Charles

  • 0 in reply to Charles Roberson
    Intellectual 261 points

    Hi Charles,

    I think it is in default Bank Mode which is Bank Mode 1, but when I try programming the BANKMGMT just to ensure it, the CCS reported this:

    Is this chip locked? What operation would cause a chip lock?

    The .out is from the project combined_services_demo imported from TIFS SDK and is built within CCS using FLASH_HSSE configuration choice. Please refer below attachment.

    FLASH_HSSE.zip

    Best Regards,

    Cesc

  • 0 in reply to Cesc Yang
    TI__Genius 15080 points

    Hi Cesc,

    Can you enable the "Verbose Output" checkbox at the bottom of the Flash Settings tool?

    I don't believe the chip to be locked. Was the "Bank Mode 1" option selected before "Program BankMGMT" button was used?

    On the current Bank Mode for the device, can you confirm on the HSSE Bank Mode in the Registers View?

    Will refer to the attachment provided and let you know on the usage more tomorrow.

    Also, is this through usage of CCS 20.3.0 release?

    Thanks and regards,

    Charles

  • 0 in reply to Charles Roberson
    Intellectual 261 points

    Hi Charles,

    Enabled verbose output and below is the output log:

    Yes the option is selected before clicking Program BankMGMT button.

    Here is the Register for Bank Mode:

    It appears to be in Bank Mode 3.  Also I noticed BANKMODE_LOCK is 1. Is this expected?

    This is done through CCS 20.1.1, but APP images also fail to be programmed on the flash even if I use the uartProgrammer.exe with uartFlashKernel.

    Thanks for you help!

    Best Regards,

    Yang

  • 0 in reply to Cesc Yang
    TI__Genius 15080 points

    Hi,

    Can you try with the latest F29-SDK and CCS 20.3.0? For Bank Mode Lock, I'll be able to see more to this inquiry by tomorrow's time. Thanks for your patience on this issue.

    Regards,

    Charles

  • 0 in reply to Cesc Yang
    TI__Genius 15080 points

    Hi Yang,

    I need to add that a BANK MODE register value of 0x3 correlates to User Bank Mode 0. So the device still needs to be placed in Bank Mode 1 by selecting the BANK Config option for '1' in the Flash Properties for the CPU Core and pressing the 'PROGRAM BANKMGMT' button. More information about device bank modes can be found in the device TRM.

    BANK MODE register values vs. User Bank Mode:

    0x3 - Bank Mode 0

    0x6 - Bank Mode 1

    0x9 - Bank Mode 2

    0xC - Bank Mode 3

    Thanks and regards,

    Charles

  • 0 in reply to Charles Roberson
    Intellectual 261 points

    Hi Charles,

    I tried configuring the BANK MODE on CCS 20.3.0, and got the same error log as before. Please see below figure.

    Right now I have several chips with this same issue once their life-cycle got set as HS-SE, not sure what's the cause. It would help a lot if I can get some info about the flash lock mechanism.

    Best Regards,

    Cesc

  • 0 in reply to Cesc Yang
    TI__Expert 6545 points

    Hi Cesc, 

    Can you send a screenshot of the BANKMGMT regions (0x10D80000, 0x10D840000, 0x10D88000, and 0x10D8C000) in the memory browser?

    Kind regards,

    Skyler

  • 0 in reply to Skyler Baumer
    Intellectual 261 points

    Hi Skyler,

    After connecting to the CPU1, these regions in the memory browser appear to be inaccessible.

    Is this abnormal?

    Best Regards,

    Yang

  • 0 in reply to Cesc Yang
    TI__Expert 6545 points

    Hi Yang,

    Are you able to view other areas of flash/RAM? Are you able to view non-SSU related registers? For example, can you show the contents of the flash registers (FRI_CTRL_REGS, FLASH_CMD_REGS_FLCx, etc.)?

    Kind regards,

    Skyler

  • 0 in reply to Skyler Baumer
    Intellectual 261 points

    Hi Skyler,

    Apologies for delay of feedback due to holidays.

    I can't access any flash areas but RAM is okay. As for registers like FRI_CTRL_REGS, FLASH_CMD_REGS_FLCx, yes they appear to be accessible on CCS.

    Since I have several chips end up in this same condition, it has become quite important for me to get more information about what kind of operation would cause this before activate HS-SE state on another chip.

    Best Regards,

    Yang

  • +1 in reply to Cesc Yang
    TI__Expert 6545 points

    Hi Yang,

    How was this device transitioned from the HS-FS to HS-SE state? Which SECCFG image was used to do this? 

    Which boot mode is configured? Can you send the contents of the SSU_GEN_REG registers?

    Kind regards,

    Skyler

  • 0 in reply to Skyler Baumer
    Intellectual 261 points

    Hi Skyler,

    I believe it's because I skipped the seccfg programming on other chips after the HS-SE transition on the first chip, and the problem no longer appears with the correct process using the latest version SDKs and CCS. 

    Best Regards,

    Yang