TMS320F28379D: Secure TMS320F283789D

Dhaval Shah

Part Number: TMS320F28379D
Other Parts Discussed in Thread: UNIFLASH, SYSCONFIG

Tool/software:

I am working on TMS320F28379D. I am having two .out files for CPU1 and CPU2. I want to secure my flash from reading by third party. I have attached my command file of CPU1 and CPU2. Please have a look and let me know what modifications needed to secure my code of CPU1 and CPU2. I am using UNIFLASH to burn code in flash.

/* Command file for CPU2*/
MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x0000A2, length = 0x00035E
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET       		: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000A0     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5          : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   	GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WdRegs         : origin = 0x00007000, length = 0x00003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHN      PAGE = 0, ALIGN(8)
   .text               : >> FLASHH | FLASHI | FLASHJ | FLASHK | FLASHL | FLASHM       PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1

   /* Initalized sections go in Flash */
   .switch             : > FLASHG      PAGE = 0, ALIGN(8)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   
#if defined(__TI_EABI__)
   .init_array         : > FLASHG,       PAGE = 0,       ALIGN(8)
   .bss                : >> RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMD0      PAGE = 0
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHG,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHG,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHG       PAGE = 0, ALIGN(8)
#endif

   /*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHG,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHG,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHG,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

	GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   	GpioDataRegsFile:	load = GPIODAT      PAGE = 1

    IpcRegsFile:		load = IpcRegs      PAGE = 1
	PieVectRegsFile:		load = PieVectRegs      PAGE = 1
	PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   	SHARERAMGS0:		load = RAMGS0      PAGE = 1
	SHARERAMGS1:		load = RAMGS1      PAGE = 1
	SHARERAMGS2:		load = RAMGS2      PAGE = 1

	WdRegsFile:		load = WdRegs      PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

/* Command file for CPU 1*/
MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   //FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

	Z1OTP_LINKPOINTER : origin = 0x078000, length = 0x000002
	Z1OTP_ZSB         : origin = 0x078020, length = 0x000008  /* First 4 fields only */
	Z1OTP_CSMPSWD     : origin = 0x078028, length = 0x000008  /* Password fields */

	Z2OTP_LINKPOINTER : origin = 0x078200, length = 0x000002
	Z2OTP_ZSB         : origin = 0x078220, length = 0x000008  /* First 4 fields only */
	Z2OTP_CSMPSWD     : origin = 0x078228, length = 0x000008  /* Password fields */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD       PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1

	Z1_LINKPOINTER 	: load = Z1OTP_LINKPOINTER PAGE = 0
	Z1_ZSB  		: load = Z1OTP_ZSB PAGE = 0
	Z1_CSMPSWD		: load = Z1OTP_CSMPSWD PAGE = 0

	Z2_LINKPOINTER 	: load = Z2OTP_LINKPOINTER PAGE = 0
	Z2_ZSB  		: load = Z2OTP_ZSB PAGE = 0
	Z2_CSMPSWD		: load = Z2OTP_CSMPSWD PAGE = 0
   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}

--retain="*(Z1_LINKPOINTER)"
--retain="*(Z1_ZSB)"
--retain="*(Z1_CSMPSWD)"

--retain="*(Z2_LINKPOINTER)"
--retain="*(Z2_ZSB)"
--retain="*(Z2_CSMPSWD)"

5 months ago

0 Luke Jones 5 months ago

TI__Mastermind 28580 points

Hi Dhaval,

I would recommend using SysConfig to program your desired DCSM settings, or to atleast generate a reference dcsm.cmd and dcsm.asm file that you can use as a reference to modify your main linker file as needed.

Thank you,

Luke

0 Dhaval Shah 5 months ago in reply to Luke Jones

Prodigy 40 points

Thanks for suggestion. I used SysConfig to tool to configure DCSM. It was successfully secured my code. But it was lock permanently. I want to secure my code in manner like if I want to reprogram controller with same .out files, it should be done by unlocking controller with proper key and it should be reprogram again. I have attached my .asm file and command file generated by SysConfig tool. Please refer it and let me know which setting make it lock permanently.dcsmPassword.asm

Fullscreen 0636.2837xD_FLASH_lnk_cpu1.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */

   /* Z1 OTP.  LinkPointers */
   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
   /* Z1 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z1_GPREG         : origin = 0x7800C, length = 0x000004
   /* Z1 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
   /* Z1 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
   /* Z1 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z1_JTAGLOCK	    : origin = 0x78018, length = 0x000004
   /* Z1 OTP.  RESERVED/BOOTCTRL */
   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004

   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010

   /* Z2 OTP.  LinkPointers */
   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
   /* Z2 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z2_GPREG	    : origin = 0x7820C, length = 0x000004
   /* Z2 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
   /* Z2 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
   /* Z2 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z2_JTAGLOCK	    : origin = 0x78218, length = 0x000004
   /* Z2 OTP.  GPREG3/BOOTCTRL */
   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004

   /* DCSM Z2 Zone Select Contents (!!Movable!!) */
   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1

   dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0
   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0
   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0
   dcsm_otp_z1_jtaglock     : > DCSM_OTP_Z1_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0

   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0
   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0
   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0
   dcsm_otp_z2_jtaglock     : > DCSM_OTP_Z2_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0

   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}

Fullscreen 0636.2837xD_FLASH_lnk_cpu2.txt Download

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x0000A2, length = 0x00035E
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET       		: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000A0     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5          : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   	GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WdRegs         : origin = 0x00007000, length = 0x00003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHG      PAGE = 0, ALIGN(8)
   .text               : >> FLASHH | FLASHI | FLASHJ | FLASHK       PAGE = 0, ALIGN(8)
  // .text               : >> FLASHC | FLASHD | FLASHE | FLASHF | FLASHG      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1

   /* Initalized sections go in Flash */
   .switch             : > FLASHN      PAGE = 0, ALIGN(8)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   
#if defined(__TI_EABI__)
   .init_array         : > FLASHN,       PAGE = 0,       ALIGN(8)
   .bss                : >> RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMD0      PAGE = 0
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHG,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHN,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHG       PAGE = 0, ALIGN(8)
#endif

   /*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHG,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHG,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHG,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

	GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   	GpioDataRegsFile:	load = GPIODAT      PAGE = 1

    IpcRegsFile:		load = IpcRegs      PAGE = 1
	PieVectRegsFile:		load = PieVectRegs      PAGE = 1
	PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   	SHARERAMGS0:		load = RAMGS0      PAGE = 1
	SHARERAMGS1:		load = RAMGS1      PAGE = 1
	SHARERAMGS2:		load = RAMGS2      PAGE = 1

	WdRegsFile:		load = WdRegs      PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Dhaval Shah 5 months ago in reply to Dhaval Shah

Prodigy 40 points

Instead of above configuration, tried step by step. Please refer attached files for reference.

1) I wanted to use GPIO42/43 as booting pin instead of GPIO72/84. So I tried "asmFIleForBootingOnly" file to configure it. it successfully set GPIO42/43 as booting pins. I tried reprogram same .out files in same controller and it successfully done and my application is also working.

2) Now I wanted to secure my flash also. So i tried "asmFile_With_Security" file to secure my flash. When I tried to load this .out file, it gives me error

[ERROR] C28xx_CPU1: Error during Flash programming (Flash algorithm returned error code). FMSTAT (STATCMD on some devices) value = 48. Operation Cancelled (0).

[ERROR] C28xx_CPU1: File Loader: Memory write failed: Unknown error

Please refer attached file and let me know what modifications needed to reprogram controller using the same .out files?

Fullscreen asmFile_With_Security.c Download

;----------------------------------------------------------------------
; Zone 1
;----------------------------------------------------------------------
     .sect "dcsm_otp_z1_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z1_bootctrl"
      .retain
      .long 0xFFFFFFFF     ;Reserved
      .long 0x2c2b0B5A

     .sect "dcsm_zsel_z1"
      .retain
      .long 0x000000FF       ;Z1-EXEONLYRAM
      .long 0x00003FC0      ;Z1-EXEONLYSECT
      .long 0x3000FFFF          ;Z1-GRABRAM
      .long 0x0FFFF555         ;Z1-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z1" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z1"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; Zone 2
;----------------------------------------------------------------------
     .sect "dcsm_otp_z2_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z2_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

;;     .sect "dcsm_otp_z2_bootctrl"
;;      .retain
;;      .long 0xFFFFFFFF     ;Reserved
;;      .long 0x49550B5A

     .sect "dcsm_zsel_z2"
      .retain
      .long 0x000000FF       ;z2-EXEONLYRAM
      .long 0x0000003F      ;z2-EXEONLYSECT
      .long 0x3000FFFF          ;z2-GRABRAM
      .long 0x05555FFF         ;z2-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z2" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z2"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; End of file
;----------------------------------------------------------------------

Fullscreen asmFIleForBootingOnly.c Download

;----------------------------------------------------------------------
; Zone 1
;----------------------------------------------------------------------
     .sect "dcsm_otp_z1_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z1_bootctrl"
      .retain
      .long 0xFFFFFFFF     ;Reserved
      .long 0x2c2b0B5A

     .sect "dcsm_zsel_z1"
      .retain
      .long 0x000000FF       ;Z1-EXEONLYRAM
      .long 0x00003FFF      ;Z1-EXEONLYSECT
      .long 0x3000FFFF          ;Z1-GRABRAM
      .long 0x0FFFFFFF         ;Z1-GRABSECT

      .long 0xFFFFFFFF
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z1" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z1"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; Zone 2
;----------------------------------------------------------------------
     .sect "dcsm_otp_z2_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z2_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

;;     .sect "dcsm_otp_z2_bootctrl"
;;      .retain
;;      .long 0xFFFFFFFF     ;Reserved
;;      .long 0x49550B5A

     .sect "dcsm_zsel_z2"
      .retain
      .long 0x000000FF       ;z2-EXEONLYRAM
      .long 0x00003FFF      ;z2-EXEONLYSECT
      .long 0x3000FFFF          ;z2-GRABRAM
      .long 0x0FFFFFFF         ;z2-GRABSECT

      .long 0xFFFFFFFF
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z2" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z2"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; End of file
;----------------------------------------------------------------------

Fullscreen 2251.CPU1_cmd.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */

   /* Z1 OTP.  LinkPointers */
   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
   /* Z1 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z1_GPREG         : origin = 0x7800C, length = 0x000004
   /* Z1 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
   /* Z1 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
   /* Z1 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z1_JTAGLOCK	    : origin = 0x78018, length = 0x000004
   /* Z1 OTP.  RESERVED/BOOTCTRL */
   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004

   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010

   /* Z2 OTP.  LinkPointers */
   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
   /* Z2 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
   /* Z2 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
   /* Z2 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
   /* Z2 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z2_JTAGLOCK	    : origin = 0x78218, length = 0x000004
   /* Z2 OTP.  GPREG3/BOOTCTRL */
   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004

   /* DCSM Z2 Zone Select Contents (!!Movable!!) */
   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1

	dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0
   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0
   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0
    dcsm_otp_z1_jtaglock    : > DCSM_OTP_Z1_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0
   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0

   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0
   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0
   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0
    dcsm_otp_z2_jtaglock    : > DCSM_OTP_Z2_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0

   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}

0 Matt Kukucka 4 months ago in reply to Dhaval Shah

TI__Genius 15760 points

Hello,

Dhaval Shah said:
2) Now I wanted to secure my flash also. So i tried "asmFile_With_Security" file to secure my flash. When I tried to load this .out file, it gives me error

Are you getting this error when programming on a fresh (i.e. unprogrammed OTP) device? That FMSTAT error (48 = 0x30) indicates that the user attempted to program a “1” where a “0” was already present.

Source: https://www.ti.com/lit/ug/spnu629/spnu629.pdf

Best,

Matt

0 Dhaval Shah 4 months ago in reply to Matt Kukucka

Prodigy 40 points

Hi,

Thanks for your reply. I was trying to use "asmFile_With_Security" file with device which was already programmed using "asmFIleForBootingOnly" file. I understand this error now.

I can try "asmFile_With_Security" file with fresh device as well. but my concern is, it should not lock my device permanently. My requirement is that I want to use GPIO42/43 for booting and secure my device flash from third party reading (Reverse Engineering). I will use UNIFLASH to load .out file in device. Also In future if I want to reprogram same device (CPU1 and CPU2) with same .out file, it should allow me to reprogram after successfully unlock using password mentioned in "

Fullscreen cmd_File_CPU1.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */

   /* Z1 OTP.  LinkPointers */
   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
   /* Z1 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z1_GPREG         : origin = 0x7800C, length = 0x000004
   /* Z1 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
   /* Z1 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
   /* Z1 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z1_JTAGLOCK	    : origin = 0x78018, length = 0x000004
   /* Z1 OTP.  RESERVED/BOOTCTRL */
   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004

   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010

   /* Z2 OTP.  LinkPointers */
   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
   /* Z2 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
   /* Z2 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
   /* Z2 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
   /* Z2 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z2_JTAGLOCK	    : origin = 0x78218, length = 0x000004
   /* Z2 OTP.  GPREG3/BOOTCTRL */
   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004

   /* DCSM Z2 Zone Select Contents (!!Movable!!) */
   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1

	dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0
   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0
   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0
    dcsm_otp_z1_jtaglock    : > DCSM_OTP_Z1_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0
   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0

   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0
   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0
   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0
    dcsm_otp_z2_jtaglock    : > DCSM_OTP_Z2_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0

   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}

Fullscreen cmd_File_CPU2.txt Download

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x0000A2, length = 0x00035E
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET       		: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000A0     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5          : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   	GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WdRegs         : origin = 0x00007000, length = 0x00003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHG      PAGE = 0, ALIGN(8)
   .text               : >> FLASHH | FLASHI | FLASHJ | FLASHK       PAGE = 0, ALIGN(8)
  // .text               : >> FLASHC | FLASHD | FLASHE | FLASHF | FLASHG      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1

   /* Initalized sections go in Flash */
   .switch             : > FLASHN      PAGE = 0, ALIGN(8)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   
#if defined(__TI_EABI__)
   .init_array         : > FLASHN,       PAGE = 0,       ALIGN(8)
   .bss                : >> RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMD0      PAGE = 0
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHG,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHN,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHG       PAGE = 0, ALIGN(8)
#endif

   /*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHG,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHG,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHG,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

	GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   	GpioDataRegsFile:	load = GPIODAT      PAGE = 1

    IpcRegsFile:		load = IpcRegs      PAGE = 1
	PieVectRegsFile:		load = PieVectRegs      PAGE = 1
	PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   	SHARERAMGS0:		load = RAMGS0      PAGE = 1
	SHARERAMGS1:		load = RAMGS1      PAGE = 1
	SHARERAMGS2:		load = RAMGS2      PAGE = 1

	WdRegsFile:		load = WdRegs      PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen asmFile_With_Security_CPU1.txt Download

;----------------------------------------------------------------------
; Zone 1
;----------------------------------------------------------------------
     .sect "dcsm_otp_z1_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z1_bootctrl"
      .retain
      .long 0xFFFFFFFF     ;Reserved
      .long 0x2c2b0B5A

     .sect "dcsm_zsel_z1"
      .retain
      .long 0x000000FF       ;Z1-EXEONLYRAM
      .long 0x00003FC0      ;Z1-EXEONLYSECT
      .long 0x3000FFFF          ;Z1-GRABRAM
      .long 0x0FFFF555         ;Z1-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z1" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z1"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; Zone 2
;----------------------------------------------------------------------
     .sect "dcsm_otp_z2_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z2_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

;;     .sect "dcsm_otp_z2_bootctrl"
;;      .retain
;;      .long 0xFFFFFFFF     ;Reserved
;;      .long 0x49550B5A

     .sect "dcsm_zsel_z2"
      .retain
      .long 0x000000FF       ;z2-EXEONLYRAM
      .long 0x0000003F      ;z2-EXEONLYSECT
      .long 0x3000FFFF          ;z2-GRABRAM
      .long 0x05555FFF         ;z2-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z2" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z2"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; End of file
;----------------------------------------------------------------------

". Please review "asmFile_With_Security" and cmd (CPU1 and CPU2) files which are attached here.

Let me know any modifications are required in attached files, So that I can reprogram my device and it does not lock permanently.

0 Matt Kukucka 4 months ago in reply to Dhaval Shah

TI__Genius 15760 points

Hello,

Are you attempting to unlock the device following the CSM password match flow detailed in the TRM? Please refer to Section 3.13.3.3 Unsecuring Considerations for Zones With and Without Code Security in the TRM.

Best,

Matt

0 Dhaval Shah 4 months ago in reply to Matt Kukucka

Prodigy 40 points

Hi Matt,

I have already refer TRM and generate "asmFile_With_Security" and cmd (CPU1 and CPU2) files according to TRM. But my doubt is whether it will lock my controller permanently? Can you please review files attached earlier and explain how it behaves? I don't want to lock my controller permanently, i want to reprogram it using same .out file by unlock it by applying key.

0 Luke Jones 4 months ago in reply to Dhaval Shah

TI__Mastermind 28580 points

Hi Dhaval,

As long as you have access to your boot mode select pins so that you can switch from flash boot to wait boot you do not need to worry about permanently locking the device. To unlock the device you may need to put the device into wait boot and then provide the CSM passwords in the On-Chip flash tool.

Thank you,

Luke

0 Dhaval Shah 4 months ago in reply to Luke Jones

Prodigy 40 points

Can you please review "asmFile_With_Security" and cmd files(CPU1 and CPU2) attached previously?

0 Luke Jones 3 months ago in reply to Dhaval Shah

TI__Mastermind 28580 points

Hi Dhaval,

I reviewed your .asm file. It seems you've selected GPIO43 and GPIO42 as your boot mode select pins and sectors A through F are designated as EXEONLY, with the rest of your sectors marked as unsecure. Is this intentional? If so I have no concerns with your config.

Thank you,

Luke

0 Dhaval Shah 3 months ago in reply to Luke Jones

Prodigy 40 points

Hi Luke,

I have used Flash A to F for CPU1 .out file and Flash G to N for CPU2 .out file. Flash A to F for Zone 1 and Flash G to N for Zone 2. Also used below configuration in .asm file to secure Flash A to F as zone 1 (.long 0x00003FC0 ;Z1-EXEONLYSECT) and Flash G to N as zone 2 (.long 0x0000003F ;z2-EXEONLYSECT). As I want to secure whole flash. Please check and let me know if I am missing anything.

.sect "dcsm_zsel_z1"
.retain
.long 0x000000FF ;Z1-EXEONLYRAM
.long 0x00003FC0 ;Z1-EXEONLYSECT
.long 0x3000FFFF ;Z1-GRABRAM
.long 0x0FFFF555 ;Z1-GRABSECT

and

.sect "dcsm_zsel_z2"
.retain
.long 0x000000FF ;z2-EXEONLYRAM
.long 0x0000003F ;z2-EXEONLYSECT
.long 0x3000FFFF ;z2-GRABRAM
.long 0x05555FFF ;z2-GRABSECT

0 Dhaval Shah 3 months ago in reply to Dhaval Shah

Prodigy 40 points

hi,

I tried program CPU1 and CPU2 using CPU1.out (Generated using CPU1_asm and CPU1_cmd) and CPU2.out (Generated using CPU2_cmd). Both .out files programmed properly step by step using Uniflash. After programming tried to read/reprogram its flash but it was not allowed because it is secured. So first I tried unlock using password and tried reprogramming with same .out files and it successfully reprogrammed. So code security feature is working now. But I configure boot control from GPIO42/43 but it was not getting boot. So my application is not working/running. Please refer attached files and let me know what I am missing in it.

Fullscreen CPU1_asm.txt Download

;----------------------------------------------------------------------
; Zone 1
;----------------------------------------------------------------------
     .sect "dcsm_otp_z1_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z1_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z1_bootctrl"
      .retain
      .long 0xFFFFFFFF     ;Reserved
      .long 0x2c2b0B5A

     .sect "dcsm_zsel_z1"
      .retain
      .long 0x000000FF       ;Z1-EXEONLYRAM
      .long 0x00003FC0      ;Z1-EXEONLYSECT
      .long 0x3000FFFF          ;Z1-GRABRAM
      .long 0x0FFFF555         ;Z1-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321

;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z1" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z1"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; Zone 2
;----------------------------------------------------------------------
     .sect "dcsm_otp_z2_linkpointer"
      .retain
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved
      .long 0x1FFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_pswdlock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

     .sect "dcsm_otp_z2_crclock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved
     .sect "dcsm_otp_z2_jtaglock"
      .retain
      .long 0xFFFFFFFF
      .long 0xFFFFFFFF     ;Reserved

;;     .sect "dcsm_otp_z2_bootctrl"
;;      .retain
;;      .long 0xFFFFFFFF     ;Reserved
;;      .long 0x49550B5A

     .sect "dcsm_zsel_z2"
      .retain
      .long 0x000000FF       ;z2-EXEONLYRAM
      .long 0x0000003F      ;z2-EXEONLYSECT
      .long 0x3000FFFF          ;z2-GRABRAM
      .long 0x05555FFF         ;z2-GRABSECT

      .long 0x12345678
      .long 0x87654321
      .long 0x12345678
      .long 0x87654321


;----------------------------------------------------------------------

; For code security operation,after development has completed, prior to
; production, all other zone select block locations should be programmed
; to 0x0000 for maximum security.
; If the first zone select block at offset 0x10 is used, the section
; "dcsm_rsvd_z2" can be used to program these locations to 0x0000.
; This code is commented out for development.

;       .sect "dcsm_rsvd_z2"
;        .loop (1e0h)
;              .int 0x0000
;        .endloop


;----------------------------------------------------------------------
; End of file
;----------------------------------------------------------------------

Fullscreen 1362.CPU1_cmd.txt Download

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x000123, length = 0x0002DD
   RAMD0           	: origin = 0x00B000, length = 0x000800
   //RAMLS0          	: origin = 0x008000, length = 0x000800
   //RAMLS1          	: origin = 0x008800, length = 0x000800
   //RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS_COMBINED : origin = 0x00008000, length = 0x00001800  /* total 8 KB from LS0–LS2 */
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

   /* Z1 OTP.  LinkPointers */
   DCSM_OTP_Z1_LINKPOINTER   : origin = 0x78000, length = 0x00000C
   /* Z1 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z1_GPREG         : origin = 0x7800C, length = 0x000004
   /* Z1 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z1_PSWDLOCK	    : origin = 0x78010, length = 0x000004
   /* Z1 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z1_CRCLOCK	    : origin = 0x78014, length = 0x000004
   /* Z1 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z1_JTAGLOCK	    : origin = 0x78018, length = 0x000004
   /* Z1 OTP.  RESERVED/BOOTCTRL */
   DCSM_OTP_Z1_BOOTCTRL	    : origin = 0x7801C, length = 0x000004

   /* DCSM Z1 Zone Select Contents (!!Movable!!) */
   /* Z1 OTP.  Z1 password locations / Flash and RAM partitioning */
   DCSM_ZSEL_Z1_P0	        : origin = 0x78020, length = 0x000010

   /* Z2 OTP.  LinkPointers */
   DCSM_OTP_Z2_LINKPOINTER	: origin = 0x78200, length = 0x00000C
   /* Z2 OTP.  GPREG1/GPREG2 */
   DCSM_OTP_Z2_GPREG	        : origin = 0x7820C, length = 0x000004
   /* Z2 OTP.  PSWDLOCK/RESERVED */
   DCSM_OTP_Z2_PSWDLOCK	    : origin = 0x78210, length = 0x000004
   /* Z2 OTP.  CRCLOCK/RESERVED */
   DCSM_OTP_Z2_CRCLOCK	    : origin = 0x78214, length = 0x000004
   /* Z2 OTP.  RESERVED/JTAGLOCK */
   DCSM_OTP_Z2_JTAGLOCK	    : origin = 0x78218, length = 0x000004
   /* Z2 OTP.  GPREG3/BOOTCTRL */
   DCSM_OTP_Z2_BOOTCTRL	    : origin = 0x7821C, length = 0x000004

   /* DCSM Z2 Zone Select Contents (!!Movable!!) */
   /* Z2 OTP.  Z2 password locations / Flash and RAM partitioning  */
   DCSM_ZSEL_Z2_P0	        : origin = 0x78220, length = 0x000010
//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000121     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5      : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   EPWM1:		origin = 0x004000, length = 0x000100    /* epwm1 registers */
   EPWM2:		origin = 0x004100, length = 0x000100    /* epwm1 registers */
   EPWM3:		origin = 0x004200, length = 0x000100    /* epwm1 registers */
   CAP1:		origin = 0x005000, length = 0x000020    /* ecap1 registers */

//   RAMGS11     : origin = 0x017000, length = 0x000FF8   /* Uncomment for F28374D, F28376D devices */

//   RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RAMGS11     : origin = 0x017000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS12     : origin = 0x018000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS13     : origin = 0x019000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

	CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
	CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WD_REG         : origin = 0x00007000, length = 0x0000003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF     PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT

#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : > RAMLS5,       PAGE = 1
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1

   /* Initialized sections in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initialized sections go in Flash */
   .econst             : >> FLASHF      PAGE = 0, ALIGN(8)
#endif

	/*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/
   /* Section for RAM functions */
   /* This section will be used by functions marked with __attribute__((ramfunc)) */
   .TI.ramfunc         : {}
                         LOAD = FLASHD,
                         RUN = RAMLS_COMBINED,
                         LOAD_START(RamfuncsLoadStart),
                         LOAD_SIZE(RamfuncsLoadSize),
                         LOAD_END(RamfuncsLoadEnd),
                         RUN_START(RamfuncsRunStart),
                         RUN_SIZE(RamfuncsRunSize),
                         RUN_END(RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)

   /* The following sections are for shared memory between CPU1 and CPU2 */
   GROUP : > CPU1TOCPU2RAM, PAGE = 1
   {
       PUTBUFFER
       PUTWRITEIDX
       GETREADIDX
   }

   GROUP : > CPU2TOCPU1RAM, PAGE = 1
   {
       GETBUFFER :    TYPE = DSECT
       GETWRITEIDX :  TYPE = DSECT
       PUTREADIDX :   TYPE = DSECT
   }

   GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   GpioDataRegsFile:	load = GPIODAT      PAGE = 1

   ePWM1RegsFile:	load = EPWM1		PAGE = 1
   ePWM2RegsFile:	load = EPWM2		PAGE = 1
   ePWM3RegsFile:	load = EPWM3		PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   cap1RegsFile:	load = CAP1      PAGE = 1

   IpcRegsFile:		load = IpcRegs      PAGE = 1
   PieVectRegsFile:		load = PieVectRegs      PAGE = 1
   PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   SHARERAMGS0:		load = RAMGS0      PAGE = 1
   SHARERAMGS1:		load = RAMGS1      PAGE = 1
   SHARERAMGS2:		load = RAMGS2      PAGE = 1

   WdRegsFile:		load = WD_REG      PAGE = 1


   dcsm_otp_z1_linkpointer 	: > DCSM_OTP_Z1_LINKPOINTER		PAGE = 0
   dcsm_otp_z1_pswdlock		: > DCSM_OTP_Z1_PSWDLOCK		PAGE = 0
   dcsm_otp_z1_crclock		: > DCSM_OTP_Z1_CRCLOCK			PAGE = 0
   dcsm_otp_z1_jtaglock     : > DCSM_OTP_Z1_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z1_bootctrl		: > DCSM_OTP_Z1_BOOTCTRL		PAGE = 0
   dcsm_zsel_z1				: > DCSM_ZSEL_Z1_P0				PAGE = 0

   dcsm_otp_z2_linkpointer	: > DCSM_OTP_Z2_LINKPOINTER		PAGE = 0
   dcsm_otp_z2_pswdlock		: > DCSM_OTP_Z2_PSWDLOCK		PAGE = 0
   dcsm_otp_z2_crclock		: > DCSM_OTP_Z2_CRCLOCK			PAGE = 0
   dcsm_otp_z2_jtaglock     : > DCSM_OTP_Z2_JTAGLOCK        PAGE = 0, type = DSECT
   dcsm_otp_z2_bootctrl		: > DCSM_OTP_Z2_BOOTCTRL		PAGE = 0, type = DSECT
   dcsm_zsel_z2				: > DCSM_ZSEL_Z2_P0				PAGE = 0

   /* Debugging symbols for CPU1 */
   /*.debug_CPU1         : > RAMM0,       PAGE = 1
   .debug_data         : > RAMD0,       PAGE = 1*/
}

Fullscreen 1362.CPU2_cmd.txt Download

MEMORY
{
PAGE 0 :
   /* BEGIN is used for the "boot to SARAM" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000002
   RAMM0           	: origin = 0x0000A2, length = 0x00035E
   RAMD0           	: origin = 0x00B000, length = 0x000800
   RAMLS0          	: origin = 0x008000, length = 0x000800
   RAMLS1          	: origin = 0x008800, length = 0x000800
   RAMLS2      		: origin = 0x009000, length = 0x000800
   RAMLS3      		: origin = 0x009800, length = 0x000800
   RAMLS4      		: origin = 0x00A000, length = 0x000800
   RAMGS14          : origin = 0x01A000, length = 0x001000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */
   RAMGS15          : origin = 0x01B000, length = 0x000FF8     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

//   RAMGS15_RSVD     : origin = 0x01BFF8, length = 0x000008    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

   RESET       		: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080002, length = 0x001FFE	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x001FF0	/* on-chip Flash */

//   FLASHN_RSVD     : origin = 0x0BFFF0, length = 0x000010    /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */

PAGE 1 :

   BOOT_RSVD       : origin = 0x000002, length = 0x0000A0     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x0003F8     /* on-chip RAM block M1 */
//   RAMM1_RSVD      : origin = 0x0007F8, length = 0x000008     /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS5          : origin = 0x00A800, length = 0x000800

   RAMGS0      : origin = 0x00C000, length = 0x001000
   RAMGS1      : origin = 0x00D000, length = 0x001000
   RAMGS2      : origin = 0x00E000, length = 0x001000
   RAMGS3      : origin = 0x00F000, length = 0x001000
   RAMGS4      : origin = 0x010000, length = 0x001000
   RAMGS5      : origin = 0x011000, length = 0x001000
   RAMGS6      : origin = 0x012000, length = 0x001000
   RAMGS7      : origin = 0x013000, length = 0x001000
   RAMGS8      : origin = 0x014000, length = 0x001000
   RAMGS9      : origin = 0x015000, length = 0x001000
   RAMGS10     : origin = 0x016000, length = 0x001000
   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

	GPIOMUX: 		origin = 0x007C00, length = 0x000180    /* GPIO mux registers */
   	GPIODAT: 		origin = 0x007F00, length = 0x000030    /* GPIO data registers */
   IpcRegs         : origin = 0x00050000, length = 0x000024    /* IPC Registers */
	PieVectRegs         : origin = 0x00000D00, length = 0x000200    /* PieVect Registers */
	PieCtrlRegs         : origin = 0x00000CE0, length = 0x000020    /* PieVect Registers */

	WdRegs         : origin = 0x00007000, length = 0x00003F
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF      PAGE = 0, ALIGN(8)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE       PAGE = 0, ALIGN(8)
  // .text               : >> FLASHC | FLASHD | FLASHE | FLASHF | FLASHG      PAGE = 0, ALIGN(8)
   codestart           : > BEGIN       PAGE = 0, ALIGN(8)

   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1        PAGE = 1

   /* Initalized sections go in Flash */
   .switch             : > FLASHB      PAGE = 0, ALIGN(8)
   .reset           : > RESET,     PAGE = 0, TYPE = DSECT /* not used, */
   
#if defined(__TI_EABI__)
   .init_array         : > FLASHB,       PAGE = 0,       ALIGN(8)
   .bss                : >> RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4 | RAMD0      PAGE = 0
   .bss:output         : > RAMLS3,       PAGE = 0
   .bss:cio            : > RAMLS5,       PAGE = 1
   .data               : > RAMLS5,       PAGE = 1
   .sysmem             : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(8)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(8)
   .ebss               : >> RAMLS5 | RAMGS3 | RAMGS4,    PAGE = 1
   .esysmem            : > RAMLS5,       PAGE = 1
   .cio                : > RAMLS5,       PAGE = 1
   /* Initalized sections go in Flash */
   .econst             : >> FLASHF       PAGE = 0, ALIGN(8)
#endif

   /*SHARERAMGS0		: > RAMGS0,		PAGE = 1
   SHARERAMGS1		: > RAMGS1,		PAGE = 1
   SHARERAMGS2		: > RAMGS2,		PAGE = 1*/

#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMLS0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(8)
        #else
            .TI.ramfunc : {} LOAD = FLASHD,
                             RUN = RAMLS0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(8)
        #endif
    #else
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMLS0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(8)
    #endif
#endif

   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

	GpioMuxRegsFile:	load = GPIOMUX		PAGE = 1
   	GpioDataRegsFile:	load = GPIODAT      PAGE = 1

    IpcRegsFile:		load = IpcRegs      PAGE = 1
	PieVectRegsFile:		load = PieVectRegs      PAGE = 1
	PieCtrlRegsFile:		load = PieCtrlRegs      PAGE = 1

   	SHARERAMGS0:		load = RAMGS0      PAGE = 1
	SHARERAMGS1:		load = RAMGS1      PAGE = 1
	SHARERAMGS2:		load = RAMGS2      PAGE = 1

	WdRegsFile:		load = WdRegs      PAGE = 1
}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

0 Dhaval Shah 3 months ago in reply to Dhaval Shah

Prodigy 40 points

Hi,

Waiting for your comments

0 Matt Kukucka 2 months ago in reply to Dhaval Shah

TI__Genius 15760 points

Hello,

Apologies for the delay, I will take over this thread since Luke has been busy.

Did you intend for these flash regions to be execute-only? When the Execute-Only protection is turned on for any secure Flash sector or RAM block, data reads to that Flash sectors are disallowed from any code (even from secure code). This could cause issues with during application runtime.

Best,

Matt

C2000™︎ microcontrollers

C2000 microcontrollers forum

TMS320F28379D: Secure TMS320F283789D