Part Number: TMS320F28377D
Other Parts Discussed in Thread: C2000WARE
Tool/software:
Hi experts
Customer has some questions about DSP:
1. About epwm trip recovery issues,
2. Don't know how to safely clear the trip,
3. Would like to ask what the operation epwm inside after OST clear, the official manual does not explain
The specific description below:
Code changes: The CC value of the original PWM was updated with the shadow register at CTR = 0, and the original interrupt was only generated at CTR = 0. Later the CC value is updated through the shadow register at CTR = 0 and CTR = PRD, and interrupts are generated at CTR = 0 and CTR = 1.
Problem Generation: The OST is forced to trigger at initialization, cleared after the conditions are met in the interrupt to generate a PWM wave, in the original configuration, the OST is cleared in the interrupt. When only one interrupt is triggered, PWM wave timing is not an issue. However, after modifying the EPWM configuration, there are times when PWM wave timing does not match the expectation, by querying the data, there is a description When CTRL_DIR = 0 clears the OST, a reset signal is generated. The CTR that decrements the 2500 count to 0 immediately and instantaneously decreases to 0, so the resulting PWM wave timing is not as expected. But when I restricted CTRL_DIR = 1, clearing the OST, there is still a probability that the cleanup will occur at CTR = 0, and it will focus on the GPIO ports of the two PWM waves EPWM5 and EPWM6. It was originally suspected that there was an error in the execution time, which caused the program to be executed at CTRL_DIR = 1, but the hardware only responded at CTRL_DIR = 0, so there was a limitation in the ISR service function. However, unexpected PWM timing is still occasionally observed. Since the application scenario is very strict with timing requirements and must be in, please ask what methods are available to make OST safe to clear.
Steps to clear OST in ISR:
Initial configuration is software tripping:
The CTR reading from EPWM1 to EPWM6 at the time of the error
Correct first PWM wave
Wrong first PWM wave, software shut off after hardware detected
PWM is configured as follows:
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Stop all the TB clocks
EDIS;
// Setup Sync
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // TBCTR=0时输出同步
// EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.PHSEN= 0; // Master module
EPwm1Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置 3750
EPwm1Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
EPwm1Regs.CMPA.bit.CMPA = 2600; // Set compare A value
// Setup counter mode
EPwm1Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm1Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm1Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = 2; // Set PWM1A on event A, up count 高有效
EPwm1Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
EPwm1Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = 1; // Active Low complementary
EPwm1Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm1Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm1Regs.TZCTL.bit.TZA = 1; //HIGH
EPwm1Regs.TZCTL.bit.TZB = 1; //HIGH
EPwm1Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = 3; // Select INT on Zero event 下溢中断
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT 使能中断
EPwm1Regs.ETPS.bit.INTPRD = 1; // Generate INT on 1rd event
// Setup Sync
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // 输出同步EPWMxSYNC同步信号
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.PHSEN= 1; // Slave module
EPwm2Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置
EPwm2Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
// EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm2Regs.CMPA.bit.CMPA = 0; // Set compare A value
// Setup counter mode
EPwm2Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm2Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm2Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm2Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = 2; // Set PWM2A on event A, up count 高有效
EPwm2Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
// EPwm2Regs.AQCTLA.bit.ZRO = 1; // Clear PWM1A on event A
EPwm2Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm2Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = 1; // Active Hi complementary
EPwm2Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm2Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm2Regs.TZCTL.bit.TZA = 1; //High
EPwm2Regs.TZCTL.bit.TZB = 1; //High
EPwm2Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
// Setup Sync
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0; // 输出同步EPWMxSYNC同步信号
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.PHSEN= 1; // Slave module
EPwm3Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置
EPwm3Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
// EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm3Regs.CMPA.bit.CMPA = 2600; // Set compare A value
// Setup counter mode
EPwm3Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm3Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm3Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm3Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm3Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = 2; // Set PWM2A on event A, up count 高有效
EPwm3Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
// EPwm2Regs.AQCTLA.bit.ZRO = 1; // Clear PWM1A on event A
EPwm3Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm3Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = 1; // Active Hi complementary
EPwm3Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm3Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm3Regs.TZCTL.bit.TZA = 1; //High
EPwm3Regs.TZCTL.bit.TZB = 1; //High
EPwm3Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
// Setup Sync
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // 输出同步EPWMxSYNC同步信号
EPwm4Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.PHSEN= 1; // Slave module
EPwm4Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置
EPwm4Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
// EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm4Regs.CMPA.bit.CMPA = 0; // Set compare A value
// Setup counter mode
EPwm4Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm4Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm4Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm4Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm4Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm4Regs.AQCTLA.bit.CAU = 2; // Set PWM2A on event A, up count 高有效
EPwm4Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
// EPwm2Regs.AQCTLA.bit.ZRO = 1; // Clear PWM1A on event A
EPwm4Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm4Regs.DBCTL.bit.POLSEL = 1; // Active Hi complementary
EPwm4Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm4Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm4Regs.TZCTL.bit.TZA = 1; //High
EPwm4Regs.TZCTL.bit.TZB = 1; //High
EPwm4Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
// Setup Sync
EPwm5Regs.TBCTL.bit.SYNCOSEL = 0; // 输出同步EPWMxSYNC同步信号
EPwm5Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm5Regs.TBCTR = 0x0000; // Clear counter
EPwm5Regs.TBCTL.bit.PHSEN= 1; // Slave module
EPwm5Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置
EPwm5Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
// EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm5Regs.CMPA.bit.CMPA = 2600; // Set compare A value
// Setup counter mode
EPwm5Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm5Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm5Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm5Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm5Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm5Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm5Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm5Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm5Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm5Regs.AQCTLA.bit.CAU = 2; // Set PWM2A on event A, up count 高有效
EPwm5Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
// EPwm2Regs.AQCTLA.bit.ZRO = 1; // Clear PWM1A on event A
EPwm5Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm5Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm5Regs.DBCTL.bit.POLSEL = 1; // Active Hi complementary
EPwm5Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm5Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm5Regs.TZCTL.bit.TZA = 1; //High
EPwm5Regs.TZCTL.bit.TZB = 1; //High
EPwm5Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
// Setup Sync
EPwm6Regs.TBCTL.bit.SYNCOSEL = 0; // 输出同步EPWMxSYNC同步信号
EPwm6Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm6Regs.TBCTR = 0x0000; // Clear counter
EPwm6Regs.TBCTL.bit.PHSEN= 1; // Slave module
EPwm6Regs.TBPRD = 2500; // frequency 20K 周期寄存器设置
EPwm6Regs.TBCTL.bit.PRDLD= 0; //通过影子寄存器装载
// Set Compare values
// EPwm2Regs.CMPA.half.CMPA = 0; // Set compare A value
EPwm6Regs.CMPA.bit.CMPA = 0; // Set compare A value
// Setup counter mode
EPwm6Regs.TBCTL.bit.FREE_SOFT = 0; // 仿真时计数停止
EPwm6Regs.TBCTL.bit.CTRMODE = 2; // Count up and down
EPwm6Regs.TBCTL.bit.PHSEN = 0; // Disable phase loading
EPwm6Regs.TBCTL.bit.HSPCLKDIV = 1; // Clock ratio to SYSCLKOUT
EPwm6Regs.TBCTL.bit.CLKDIV = 0;
// Setup shadowing
EPwm6Regs.CMPCTL.bit.SHDWAMODE = 0; //通过影子寄存器装载
EPwm6Regs.CMPCTL.bit.SHDWBMODE = 0; //通过影子寄存器装载
EPwm6Regs.CMPCTL.bit.LOADAMODE = 2; // Load on Zero
EPwm6Regs.CMPCTL.bit.LOADBMODE = 2; // Load on Zero
// Set actions
EPwm6Regs.AQCTLA.bit.CAU = 2; // Set PWM2A on event A, up count 高有效
EPwm6Regs.AQCTLA.bit.CAD = 1; // Clear PWM1A on event A, down count
// EPwm2Regs.AQCTLA.bit.ZRO = 1; // Clear PWM1A on event A
EPwm6Regs.DBCTL.bit.IN_MODE = 0; // EPWM1A as source
EPwm6Regs.DBCTL.bit.OUT_MODE = 3; // enable Dead-band module
EPwm6Regs.DBCTL.bit.POLSEL = 1; // Active Hi complementary
EPwm6Regs.DBRED.bit.DBRED= 75; // FED = 100 TBCLKs 1us 200/200M
EPwm6Regs.DBFED.bit.DBFED= 75; // RED = 100 TBCLKs 1us
// Trip set
EALLOW;
EPwm6Regs.TZCTL.bit.TZA = 1; //High
EPwm6Regs.TZCTL.bit.TZB = 1; //High
EPwm6Regs.TZFRC.bit.OST = 1; //强制触发Trip
EDIS;
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Start all the timers synced 3dspli 需通过CPLD来同步
EDIS;
