TMS320F28379D: Unable to update DBCTL in Global Shadow Mode upon SYNC generation

Hello,

Could you please check what is your DBCTL register bitfield values in CCS during the run-time, specifically SHDWDBFEDMODE and SHDWDBREDMODE registers? That would give you good insight if they DBCTL is configured correctly.

Also there is a note in device TRM, page 1945: https://www.ti.com/lit/ug/spruhm8k/spruhm8k.pdf. that states:

"The application software must enable shadow load mode in the DBCTL[SHDWDBREDMODE] and DBCTL[SHDWDBFEDMODE] before programming values for the DBRED and DBFED registers. If the shadow register is enabled after programming the DBRED and DBFED registers, the DBRED and DBFED registers are loaded with a value of 0."

Hello Stevan,

Thanks for your reply. We will check the shadow mode register bits in CCS during run time. However, the code configuring the dead band module is as follows:

// Dead Band Module Configuration (DBCTL, DBRED, DBFED)
          EPwm1Regs.DBCTL2.bit.SHDWDBCTLMODE = 1; // shadow mode - not sure if needed for successful global shadow to active loading - taking precaution
          EPwm1Regs.DBCTL2.bit.LOADDBCTLMODE = 0; // shadow to active loading of FED at CTR = 0

          EPwm1Regs.DBCTL.bit.HALFCYCLE = 0; // dead-band counters are clocked at TBCLK
          EPwm1Regs.DBCTL.bit.POLSEL = 0; // neither PWM is inverted after RED FED incorporation

          EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 1; // shadow mode - not sure if needed for successful global shadow to active loading - taking precaution
          EPwm1Regs.DBCTL.bit.LOADREDMODE = 0; // shadow to active loading of RED at CTR = 0
          EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 1; // shadow mode - not sure if needed for successful global shadow to active loading - taking precaution
          EPwm1Regs.DBCTL.bit.LOADFEDMODE = 0; // shadow to active loading of FED at CTR = 0

First, I enable the shadow mode bit in DBCTL2, then I initialize the DBCTL register bits (including SHDWREDMODE and SHDWFEDMODE). This is done in main() and the DBRED & DBFED registers are updated only in the ISR which begins after main() has been executed (in the ISR). Thus, in theory, I believe the code is in compliance with the TRM note on page 1945.

Might the issue be related to the DBCTL2 register? Because I am pretty sure DBRED and DBFED are getting updated upon global SYNC only (I will re-confirm this).

Hello,

Yes, checking registers in CCS will clarify if they are set up as desired. Maybe configuring DBCTL first register would help. By the way, are you using Global Load feature in your software?

Hi,

Yes, I am using global load, configured to perform global shadow-to-active load when SYNC is generated. Hence, I was confused if the DBCTL2 and DBCTL[SHDWREDMODE] registers are needed to be configured, because they are for local shadow-to-active loading, right?

Also, by configuring DBCTL first, do you mean setting DBCTL2 after DBCTL in the code snippet above? Will try this, but my rationale was that the shadow-mode bit should be enabled before configuring the register as per the note, page 1945, TRM

Hello Tharun,

There is a note in device TRM, page 1945 about DBRED/DBFED when using global load support that could apply to your case: 

"When DBRED/DBFED active is loaded with a new shadow value while DB counters are counting, the new DBRED/DBFED value only affects the NEXT PWMx edge and not the current edge. A Deadband value of zero cannot be used when the Global Shadow to Active Load is set to occur at CTR=ZERO. Similarly, a Deadband value of PRD cannot be used when the Global Shadow to Active Load is set to occur at CTR=PRD."

Hi Stevan,

In the code, I have ensured that the SYNCEVT is not generated at any PWM edge but in between the PWM edges, so I doubt that is the issue. What do you think about the fact that the DBCTL bit is getting updated in immediate mode despite configuring it for shadow mode? Can you perhaps run an experiment that configures DBCTL2 and DBCTL properly, where the register values of DBCTL, DBRED and DBFED only change when SYNCEVT is generated? If you could then share that code, it would be a great help.

Hello,

If you use the global load you need to configure an event on which all registers are updated at the same time unless it would not work. Please check if your registers are getting updated properly.

Stevan,

Kindly refer to the query description, as mentioned, I have already configured a SYNCEVT for global loading (GLDMODE = 3, along with GLDCTL and GLDCFG registers). Is there anything else I need to do?
The PWM duties and phases are clearly getting updated by global load strobe when SYNCEVT is generated (as evidenced by the figure attached). My specific problem is that DBCTL register seems to be getting updated in immediate mode, NOT as per the SYNCEVT. Kindly help.

Hello Tharun,

Thank you for your clarification. The contents of the shadow dead-band registers are transferred to the active registers on one of the following events as specified by the DBCTL [LOADREDMODE] and DBCTL [LOADFEDMODE] register bits:

• CTR = PRD: Time-base counter equal to the period (TBCTR = TBPRD).

• CTR = Zero: Time-base counter equal to zero (TBCTR = 0x00)

• Both CTR = PRD and CTR = Zero

Therefore, dead-band shadow mode does not have an option to occur on SYNC event. The shadow mode cannot be done on SYNC event and that's why it just behaves as an immediate mode operation.