TMS320F28P650DK: If I plan to use AUXPLL to provide 100M clock for CLB, how should I configure it?

Part Number: TMS320F28P650DK

Tool/software:

Hi, engineers!

I did not find any relevant designs in the routine, and there was not much introduction in the datasheet. I also did not find corresponding register descriptions for CLBCLK Divider and TILECLK Divider.
After configuring in syscfg, there is no corresponding configuration program.

Regards,
Lin Haonan

  • Hi Lin,

    The TRM would have the relevant information to registers in the System Control and CLB sections.

    In any (CLB) example (ie. clb_ex14_multi_tile), we can view the clocking configurations via the ClockTree Tool + generated device.c / device.h / clocktree.h files. To view device files, you need to enable the Device Support module. For more information on the ClockTree Tool, refer to the C2000 SysConfig: ClockTree tool Video.

    Best Regards,

    Aishwarya