TMS320F2800132: EPWM Initialization issue

Hi Sumit , Thanks for replying

Yes i have tried it that and works fine . But code snippet represents Register mapped configuration from TRM understanding . 

I tried some other configuration found it to be working  Please find the working code ,

#include "f28x_project.h"
#include "f280013x_device.h"

#define STAND_ALONE_EPWM
//
// Main
//
unsigned int i = 0;

void Gpio_ePwm(void);
void ClockConfig(void);
void init_ePWM3(void);
void start_ePWM(void);

void main(void)
{
InitSysCtrl();
InitGpio();
EALLOW;

GpioCtrlRegs.GPBGMUX1.bit.GPIO32 = 1;
GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 0;
GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO32 = 1;

EDIS;
//
// Initialize PIE and clear PIE registers. Disables CPU interrupts.
//
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
InitPieVectTable();

//
// Enable Global Interrupt (INTM) and realtime interrupt (DBGM)
//
EINT;
ERTM;

/* Step 1 : Assigns GPIO 227 Pin 20 DRIVEB --> EPWMB and GPIO 230 Pin 21 DRIVEA --> EPWM A*/
Gpio_ePwm();
/* Step 2 : Configure EPWM Clock, Disable TIME BASE CLOCK for Setting up the Registers*/
ClockConfig();
/* Step 3 : Configure Time- Base , Capture Compare , Action Qualifier Blocks*/
init_ePWM3();
/* Step 4 : Enable Time BASE CLOCk and start the ePWM Module*/
start_ePWM();

while(1)
{
// GpioDataRegs.GPASET.bit.GPIO12 = 1;
GpioDataRegs.GPBSET.bit.GPIO32 = 1;
DELAY_US(1000000);
GpioDataRegs.GPBCLEAR.bit.GPIO32 = 1;
DELAY_US(1000000);

}

}

/*GPIO Muxing Channels*/
void Gpio_ePwm(void)
{
EALLOW;
/*GPIO Muxing*/
GpioCtrlRegs.GPHMUX1.bit.GPIO227 = 3;
GpioCtrlRegs.GPHMUX1.bit.GPIO230 = 3;

GpioCtrlRegs.GPHDIR.bit.GPIO227 = 1; // output
GpioCtrlRegs.GPHDIR.bit.GPIO230 = 1; // output

GpioCtrlRegs.GPHPUD.bit.GPIO227 = 1; // Enable internal pull-up (0=enabled, 1=disabled)
GpioCtrlRegs.GPHQSEL1.bit.GPIO227 = 0; // Qualification = sync to sysclk

GpioCtrlRegs.GPHPUD.bit.GPIO230 = 1; // Enable internal pull-up (0=enabled, 1=disabled)
GpioCtrlRegs.GPHQSEL1.bit.GPIO230 = 0; // Qualification = sync to sysclk
EDIS;
}

/* ePWM Clock initialization*/
void ClockConfig(void)
{

/*
The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all enabled
ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are started with
the first rising edge of TBCLK aligned. For synchronized TBCLKs, the prescalers for each ePWM module must
be set identically.
The proper procedure for enabling ePWM clocks is as follows:
1. Enable ePWM module clocks in the PCLKCRx register
2. Set TBCLKSYNC= 0
3. Configure ePWM modules
4. Set TBCLKSYNC= 1
*/
EALLOW;
CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; // Enable EPWM3 Clock
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable Time Base Clock
EDIS;
}

void start_ePWM(void)
{
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Disable Time Base Clock
EDIS;
}

/* ePWM 3 Configurations for TB , AQ and CC block */

void init_ePWM3(void)
{
// Time Base Block Congigurations
EPwm3Regs.TBPRD = 1500 ; // Period register → sets freq
EPwm3Regs.TBCTL.bit.CTRMODE = 2 ; // Up-Down count mode

EPwm3Regs.TBCTL.bit.HSPCLKDIV = 1 ; // Clock divide = /2
EPwm3Regs.TBCTL.bit.CLKDIV = 0 ; // Clock divide = /1

#ifdef STAND_ALONE_EPWM
EPwm3Regs.EPWMSYNCINSEL.bit.SEL = 0 ; // Disable Sychronizations
EPwm3Regs.TBCTL.bit.PHSEN = 0 ; // Disable phase loading
//EPwm3Regs.TBCTL.bit.SWFSYNC = 0 ; // Disabled Software Force Sync
#endif

// Counter Compare Block Configurations

EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0 ; // Double Buffer via CPU Shadow Register
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0 ; // Double Buffer via CPU Shadow Register
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0 ; // Load to Active Register when CTR = 0
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0 ; // Load to Active Register when CTR = 0

// Action Qualifiers Block Configurations

EPwm3Regs.AQCTLA.bit.CAU = 2 ; // Set High EPWM 3A When CTR = CMPA while Up Count.
EPwm3Regs.AQCTLA.bit.CAD = 1 ; // Clear EPWM 3A When CTR = CMPA while Down Count.
//EPwm3Regs.AQCTLA.bit.PRD = 2 ;

EPwm3Regs.AQCTLB.bit.CBU = 1 ; // Clear EPWM 3B When CTR = CMPB while Up Count.
EPwm3Regs.AQCTLB.bit.CBD = 2 ; // Set High EPWM 3B When CTR = CMPB while Down Count.
// EPwm3Regs.AQCTLA.bit.ZRO = 2 ;
// Set the Compare Values (Duty Cycle)

EPwm3Regs.CMPA.bit.CMPA = 1450 ; // 50% duty for A
EPwm3Regs.CMPB.bit.CMPB = 50 ; // 25% duty for B

}