TMS320F28P650DH: UART receive idle interrupt

Part Number: TMS320F28P650DH

Tool/software:

Hi,

Customer is using F28P65 SCI and UART for external communication.

They need receive idle interrupt function on UART (SCI already has), but it doesn't have. Any solution?

For UART FIFO transmit, is there any way to support both odd and even numbers of bytes transmit interrupt?

Thanks a lot.

Br, Jordan

  • Hi Jordan,

    They need receive idle interrupt function on UART (SCI already has), but it doesn't have. Any solution?

    There is a receive timeout interrupt on UART they should be able to use in a similar manner. This interrupt flag will go high if there is data sitting in the RX FIFO for an extended period of time - meaning effectively that the RX line has gone idle and the data has finished sending (similar logic to an idle interrupt). To set this up, they could configure the RX FIFO level to be 14/16 and enable both the RX interrupt and the RT interrupt. If the ISR is entered with the RX flag high, the software can read 14 bytes from the RX FIFO. If the ISR is entered when the RT interrupt is high, software can read the RX FIFO until it is empty and perform any additional code needed for the end of the transmission. The only situation where this wouldn't work is if the transmitting device sends data in a multiple of 14. Do they know how many bytes the transmitting device will send at a time?

    For UART FIFO transmit, is there any way to support both odd and even numbers of bytes transmit interrupt?

    Unfortunately, there is no 1/16 FIFO level option on UART. The 2/16 FIFO level can be used for any even-numbered transmission. For odd numbered transmissions, they could do one of the following:

    • Disable the FIFO - with this setting, the interrupt will trigger every time the 1-byte holding register is empty and bytes can be written by software one by one.
    • Use 2/16 FIFO level and transmit all but the last byte by writing two bytes to the TX FIFO in each interrupt. They can use state variables to keep track of how many interrupts have occurred and on the last interrupt, only write one byte to the TX FIFO rather than two to complete the odd numbered transmission.

    Let me know if they have any additional questions. 

    Best Regards,

    Delaney

  • Delaney,

    Thanks for your reply.

    In receive mode, if DMA is used, timeout doesn't work, right? Every time when FIFO receives data, DMA will copy to RAM. 

    Br, Jordan

  • Hi Jordan,

    The receive timeout method could still work in this case. DMA will copy every 14 bytes to RAM (or however many bytes depending on the FIFO level and matching DMA burst size configured) and then the RT interrupt can still be used for the last x amount of bytes at the end of the transmission.

    Best Regards.

    Delaney