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Original question:

TMS320F280049C: ADC-to-DAC loopback check

TMS320F280038C-Q1: ADCDACLOOPBACK misoperation

Gokhan G.
Intellectual 765 points
Part Number: TMS320F280038C-Q1


Tool/software:

Hi,

There are some threads on the forum regarding the ADCDACLOOPBACK issue, but no clear solutions are available.

I added following lines at init and didn't change it later on. Therefore, I wanted to always measure internal biased voltage at ADC results.

1) Has an example software for the ADCDACLOOPBACK application been prepared, or will it be prepared? It is really a critical and useful function for safe operations.
2) I did a preliminary study with the following lines. However, even though I only selected ADCA at below lines, both ADCA and ADCC are set to an internal voltage. How it can be? Is my code correct?

    EALLOW;
    HWREG(ANALOGSUBSYS_BASE + 0x88U) =
            (HWREG(ANALOGSUBSYS_BASE + 0x88U) | 0x01U) |
            (0xA5A5UL << 16U);
    EDIS;

3) When I enabled all ADC modules for ADCDACLOOPBACK, the ADCA and ADCC modules reads a strange internal voltage. However, the ADCB module is not biased to an internal voltage.

ADCB didn't follow instructions. Red arrowed signals are related to ADCB.

Can you explain how it can be?


4) Even though I set the value of 4095 to the CMPSS1_DACL port, the ADCA and ADCC RESULT registers are all set to a value around ~3417.
I didn't set any DAC configuration at software. I just use CMPSS configurations which needs internal DAC to compare.

The CMPSS1 High Comparator is used for peak-current mode, and the CMPSS1 Low Comparator module is used for protection purpose. CMPSS1_DACL is as below;

  • 0
    TI__Guru* 81820 points

    Gokhan,

    There is a driverLIB function in asysctrl.h to enable this path from the internal DAC inside CMPSS1 Low side comp to the ADC.  I've C/P below; if you are using DriverLIB you can call these functions directly as shown.  

    Keep in mind that only the 6 MSB of the DAC will get used in this connection, so the resolution will be 6-bits vs when used in conjunction with the comparator.

    When this is active, any conversion of any channel on ADC A or ADC C will sample this net.

    For ADC B connection, there is a bug such that this connection does not exist for ADCB to the DAC.  This is detailed in the errata here: 

    https://www.ti.com/document-viewer/lit/html/SPRZ496D#GUID-812FA5F5-7664-4D28-A363-57F143979561/GUID-F3A6BC45-F851-4373-978C-78FB1D116EB6

    Best,

    Matthew

  • 0 in reply to MatthewPate
    Intellectual 765 points

    1) I still couldn't understand that how I get ~~3410 value at ADC results.

    DAC is 1111 1111 1111.    -> 6MSB is used: 1111 1100 0000; therefore I should get 4032.

    Is 3410 result correct?
    Can you please explain in detail?

  • 0 in reply to Gokhan G.
    TI__Guru* 81820 points

    Gokhan,

    The sample and hold duration has a higher limit than normal ADC converisions:

    The minimum sampling window size (ACQPS) when converting the DAC output is 4.27µs (512 SYSCLK cycles at 120MHz SYSCLK)

    Can you check the ACQPS setting for the SOC that is set up to sample the loopback input, to make sure it satisfies the above?

    Also, the CMPSS DAC Full Scale range is based on VDDA supply voltage.  While I doubt your VDDA = 2.75V, there could be some slight difference to the FSR and the FSR of the ADC that will need to be taken into account.

    Best,

    Matthew