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TMS320F28335: Sporadic PWM Interrupts when using PWM-SYNC

MikeP
Prodigy 70 points

Part Number: TMS320F28335

Tool/software:

Hello guys, I am struggling with some issue since some days and maybe someone can give me a hint.

We are using 2 pieces of F28335 connected with an optical cable to synchronize the PWM timers. This optical line is received with a photo diode, through an inverter and connected to GPIO6.

What we encounter is some weird behavior:

* The photo diode and also the inverter generate perfectly nice signals for GPIO6 (Sync-In), Still there are sporadic PWM-Interrupts
* The PWM-Interrupt is configured to CNT = zero, but when checking the the counter during these sporadic interrupts, it is way above zero
* The interrupts are still present when disabling Sync-In all together (in the PWM peripheral as well as with the GPIO configuration)
* Still they have some connection to the Sync-In, because depending of the (optical cable) used they appear more or less often (or not at all with some cables).

What I do not understand is, how can the PWM-Interrupt be triggered even the configured condition (CTR = zero) was clearly not met and how can I find the source of this?
Also why can the occurrence of the interrupts change depending on the Sync-In cabling when the GPIO6 does not show any sign of out-of-place signals?

I added my PWM-config for EPwm1, if you need any more details about my config, please let me know.

EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //2
EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; //1
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; //0
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; //0
 EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; //1
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; //1
EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP; //1
EPwm1Regs.TBCTL.bit.SWFSYNC = 0; 

EPwm1Regs.TBPHS.half.TBPHS = 0x0000; 
EPwm1Regs.TBPRD = 4600;
EPwm1Regs.TBCTR = 0x0000;

EPwm1Regs.CMPA.half.CMPA = 0;
EPwm1Regs.CMPB = 0;

EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_IMMEDIATE; //1
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; //1
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_IMMEDIATE; //1
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; //1

EPwm1Regs.AQCTLA.bit.ZRO = 0;
EPwm1Regs.AQCTLA.bit.PRD = 0;
EPwm1Regs.AQCTLA.bit.CAU = 0;
EPwm1Regs.AQCTLA.bit.CAD = 0;
EPwm1Regs.AQCTLA.bit.CBU = 0;
EPwm1Regs.AQCTLA.bit.CBD = 0;

EPwm1Regs.AQCTLB.bit.ZRO = 0;
EPwm1Regs.AQCTLB.bit.PRD = 0;
EPwm1Regs.AQCTLB.bit.CAU = 0;
EPwm1Regs.AQCTLB.bit.CAD = 0;
EPwm1Regs.AQCTLB.bit.CBU = 0;
EPwm1Regs.AQCTLB.bit.CBD = 0;

EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; //1
EPwm1Regs.ETSEL.bit.INTEN  = INT_ON; //1
Pwm1Regs.ETPS.bit.INTPRD  = 1;

EPwm1Regs.ETSEL.bit.SOCAEN = INT_ON; //1
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; //1
EPwm1Regs.ETSEL.bit.SOCBEN = INT_OFF; //0
EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_ZERO; //1
EPwm1Regs.ETPS.bit.SOCACNT = 1;
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
EPwm1Regs.ETPS.bit.SOCBPRD = 1;
EPwm1Regs.ETPS.bit.SOCBCNT = 1;

  • 0
    TI__Expert 7170 points

    Hello,

    I will take a look and reply in timely manner.

  • 0 in reply to Stevan Duraskovic
    Prodigy 70 points

    Thanks for your reply, we already figured out something meanwhile.

    The interrupts look like they are happening nearly at the same time (the later one just gets delayed), which means the Sync-In might have some jitter depending on the cable quality and therefore the event CTR = zero happens twice in a very short period of time (once by actually counting to zero and then again with Sync-In).

    How is general the recommendation to deal with something like this, is it advised not to put interrupts on CTR = zero in this case, when Sync-In also sets CTR to zero? One option might be to simply trigger the interrupt on CTR = <some small value> to ensure the Sync-In happened before.

    BR
    Michael

  • 0 in reply to MikeP
    TI__Expert 7170 points

    Hello,

    You have various options to trigger interrupt based on event you choose: https://www.ti.com/lit/ug/sprui07/sprui07.pdf. You could refer to device TRM page 272

    You can trigger it with CMPA value and set it up to a small value to avoid conflicts on TBCTR = zero.