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TMS320F28379D: UART on second core

Kappa
Prodigy 40 points

Part Number: TMS320F28379D

Tool/software:

Hi,

I am using SCIa on core 1 and SCIc on core 2 of 28379D. This is a test. I am trying to read data sent out by scic on second core and put data on shared memory and read on cpu1. My problem is second core jumps to RX interrupt routine just once. Interrupt does not get cleared, and then RXFFST shows 10000! I really appreciate your comment on this. The code is:

//#############################################################################
// Included Files
#include "device.h"
#include "driverlib.h"
#include "inc/hw_ipc.h"
#pragma DATA_SECTION(rxData, ".myCharArraySection2_1")
char rxData[5];
volatile bool rxComplete = false;


__interrupt void scicRxFIFOISR(void)
{
 int i;
    // Assuming RX FIFO level is 4
    int16_t fifoCount = HWREG(SCIC_BASE + SCI_FFRX_RXFFST_M);
    for (i = 0; fifoCount && i < 5; i++)
    {
        rxData[i] =  HWREG(SCIC_BASE + SCI_O_RXBUF);  // Read each byte from FIFO
        // Process each byte (e.g., store, echo, parse)
    }
    rxComplete = true;
    if(!(HWREG(IPC_BASE + IPC_O_STS) & (1UL)))
    {
        //
        HWREG(IPC_BASE + IPC_O_SET) = 1UL;
    }
    // Clear RX FIFO interrupt flag
    //i=HWREG(SCIC_BASE + SCI_O_FFRX);
    HWREG(SCIC_BASE + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR;
   // ScicRegs.SCIFFRX.bit.RXFFINTCLR = 1;  //same as above
    // Acknowledge PIE interrupt
    HWREG(PIECTRL_BASE + PIE_O_ACK) = INTERRUPT_ACK_GROUP8;
}

//
void main(void)
{
    uint32_t count;
    uint16_t state;
    uint16_t TXBSY;
    //

    Device_init();
  Interrupt_initModule();
 Interrupt_initVectorTable();
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC);
    SCI_setConfig(SCIC_BASE, 50000000, 115200, SCI_CONFIG_WLEN_8 | SCI_CONFIG_STOP_ONE | SCI_CONFIG_PAR_NONE);
    SCI_enableModule(SCIC_BASE);
    SCI_resetChannels(SCIC_BASE);
    HWREG(SCIC_BASE + SCI_O_FFTX)|=0X4000;
    HWREG(SCIC_BASE + SCI_O_FFTX)|=0X0040;
    Interrupt_register(INT_SCIC_RX, &scicRxFIFOISR);
    HWREG(SCIC_BASE + SCI_O_FFRX) =  0x6025;
    Interrupt_enable(INT_SCIC_RX);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP8);
    Interrupt_enable(INTERRUPT_CPU_INT8);
    HWREG(PIECTRL_BASE + PIE_IER8_INTX5) =  PIE_IER8_INTX5;
    HWREG(SCIC_BASE + SCI_O_FFTX)|=0x0040;
    IER |= INTERRUPT_CPU_INT8;                      // Enable CPU INT8
    EINT;
    ERTM;

    HWREG(IPC_BASE + IPC_O_SET) = 1UL << ipcFlag17;
    state = GPIO_readPin(11UL);
    GPIO_togglePin(10UL);
    while(1) {
        if(count++ > 200000)      {
            count = 0;
           // GPIO_togglePin(35U);
                 GPIO_writePin(52U, 1);
           // GPIO_setPortPins(GPIO_PORT_B, 20U);
            SCI_writeCharBlockingFIFO(SCIC_BASE, '1');
            SCI_writeCharBlockingFIFO(SCIC_BASE, '2');
            SCI_writeCharBlockingFIFO(SCIC_BASE, '3');
            SCI_writeCharBlockingFIFO(SCIC_BASE, '4');
            SCI_writeCharBlockingFIFO(SCIC_BASE, '5');
          //  GPIO_clearPortPins(GPIO_PORT_B, 20U);
         //   GpioDataRegs.GPBSET.bit.GPIO51=0;
            // Toggle GPIO10
            GPIO_togglePin(10UL);
        }
        TXBSY= (HWREGH(SCIC_BASE + SCI_O_CTL2) & SCI_CTL2_TXEMPTY);
        TXBSY=  !(((HWREGH(SCIC_BASE + SCI_O_CTL2) & SCI_CTL2_TXEMPTY) == SCI_CTL2_TXEMPTY) ? true : false);
        GPIO_writePin(52U, TXBSY);
    }
}

// End of file

Thank you

  • 0
    TI__Mastermind 26970 points

    Hello,

    Can you first check your initialization for SCI? Can you please try to initialize the SCI module in this order:

    1. First, ensure all SCI interrupts are disabled
    2. Next, clear the interrupt status of all SCI interrupts (RXFF, TXFF, FE, OE, PE, RXERR, BRKDT, TXRDY) by clearing and then setting SCI’s CTL1.SWRESET bit and setting SCI’s FFTX.TXFFINTCLR and FFRX.RXFFINTCLR bits.
    3. Next, clear the overflow status bit by setting SCI’s FFRX.RXFFOVRCLR bit
    4. Next, reset the RX and TX FIFOs by clearing and then setting the FFTX.TXFIFORESET
    5. Next, reset the TX and RX channels of the device by clearing and then setting the FFTX.SCIRST bit.
    6. Next, actually configure all the SCI settings for your system, like baud rate (SCIHBAUD+SCILBAUD registers), parity+data length+stop bits (SCICCR register).
    7. Next, enable the module by setting CTL1.TXENA, CTLA.RXENA, and CTL1.SWRESET. This also performs a software reset of the SCI module to prepare it for running.
    8. Next, if using the FIFO, set the appropriate FIFO interrupt levels by setting the levels in the FFTX.TXFFIL and FFRX.RXFFIL fields. The FIFO levels must be chosen to allow sufficient time for the interrupt to handle the data requests before FIFO overflows. For long SCI ISRs, make sure to interrupt sufficiently early, or move the processing out of the ISR and only do data movement in the SCI ISR (recommended).
    9. Finally, if using the FIFO, enable the FIFO by setting the FFTX.SCIRST (if not set, though it is safe to set again), FFTX.SCIFFENA, FFTX.TXFIFORESET, and FFRX.RSFIFORESET bits.
    10. Finally, enable the module again by setting the CTL1.TXENA, CTLA.RXENA, and CTL1.SWRESET bits. This also performs a software reset of the SCI module to prepare it for running.

    In your interrupt service routine, please check that it properly clears the interrupt flags:

    1. Read data from FIFO
    2. Clear overflow status if any
    3. Clear the RX FIFO interrupt flag
      HWREG(SCIC_BASE + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR;
    4. Clear PIE interrupt with ACK

    Please also double check that:

    • Overflow condition is being cleared properly
    • FIFO is being reset correctly during initialization
    • Interrupt flags are being cleared properly in the ISR
    • Check for any RX errors in your ISR so you can handle them

    Best Regards,

    Allison

  • 0 in reply to Allison Nguyen
    Prodigy 40 points

    Hi Allison,

    Thank you for the response.

    I did some investigation. The interrupt jumps one time to ISR, then stops going there. I halted CPU and checked;  the peripheral interrupt flag is set. PIEIFR is set. PIEIER is correctly set. CPU IER is correctly set (in core registers), however IFR does not propagate to CPU, in other word associated IFR in core register is not set. I acknowledge the interrupt is ISR and PIEACK is set correctly. It is my first time working on TI MCUs, am I missing something?

    Your help is really appreciated.

    Thank you

  • 0 in reply to Kappa
    TI__Mastermind 26970 points

    Hi,

    Thanks for the additional information - let me verify with one of our PIE experts as well based on your input.

    Best Regards,

    Allison

  • 0 in reply to Kappa
    TI__Mastermind 26970 points

    Hi,

    Thanks for your patience. Can you please send the register values (either export or screenshot) when you halt the CPU? And can you detail exactly when you are halting it? Is this within the first ISR? Or after exiting? Are you stepping through the ISR to check the ACK is being closed when you acknowledge in the PIE the first time the CPU2 goes to the ISR?

    Best Regards,

    Allison