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TMS320F28379D: TMS320F28379D

Raushan kumar
Prodigy 10 points
Part Number: TMS320F28379D


Tool/software:

I am working on firmware coding and have some questions regarding ADC signal sensing. I have three converters connected in series:

  1. Converter 1 – 3 kHz

  2. Converter 2 – 20 kHz

  3. Converter 3 – 3 kHz

Each converter has its own PWM interrupt, but I am confused about the sequence for selecting SOCs and ADC modules for each converter’s ADC sensing. The details of the ADC sampling are as follows:

Converter 1 (3 kHz):

  • Vdc – 2 samples

  • Vout – 4 samples

  • Iout – 4 samples

Converter 2 (20 kHz):

  • Vout – 4 samples

  • Transformer input current – 4 samples

Converter 3 (3 kHz):

  • Va – 4 samples

  • Vb – 4 samples

  • Ia – 4 samples

  • Ib – 4 samples

Kindly suggest how I can proceed to achieve fast ADC sensing since all converters are connected in series.

Thank you for your support and understanding.

  • 0
    TI__Expert 3890 points

    Hi Raushan,

    Converter 2 is 20 kHz, while converters 1 & 3 are 3 kHz. That means converter 2 triggers occur more frequently. You’ll need to schedule the ADC loads so the faster ADC sequence doesn’t block the slower ones. If you need to average multiple samples or do digital filtering, consider the timing for accumulating and the data dependency across tasks.

    You might use the 20 kHz converter interrupt (fastest) as the “master” trigger. Every 50 µs (20 kHz), trigger the ADC for converter 2’s measurements. Also, within that ISR (or a lower-priority ADC task), check whether this event corresponds to a sampling instant for converters 1 or 3 (since 3 kHz is slower) and every 6th or 7th 20 kHz interrupt (depending on exact division), also perform the ADC for converter 1 or converter 3.


    Because 3 kHz is ~6.67× slower than 20 kHz, you might sample converter 1 and converter 3 every 20 kHz interrupt 6 or 7 times (i.e. every Nth interrupt). E.g., sample converter 1 at interrupt counts 0, 6, 12, …, and converter 3 at counts 3, 9, 15, … (or other phase offsets) so that the extra load is spread.


    Also, use different ADC modules / SOC groups if possible, assign converter 1’s ADC needs to ADC A, converter 2 to ADC B, converter 3 to ADC C (or reuse ADC A/B if C is not available), to reduce multiplexing conflicts and within each ADC, pre-configure multiple SOC channels with proper sampling windows and triggers.


    The 20 kHz path might have tighter real-time constraints, so make sure those ADC sequences finish quickly, with minimal branching or overhead. The slower 3 kHz tasks can use “leftover” ADC time in the 20 kHz cycle.

    If you schedule too many ADCs in one interrupt, you may miss future PWM or ADC deadlines. Also, you need to ensure that shared resources (ADC input multiplexer) are not switching while conversions are ongoing.

    Best Regards,
    Masoud