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Original question:

TMS320F28075 Power Sequencing

TMS320F28075: Supply Ramp Rate above limits

Soeren Juul
Prodigy 20 points

Part Number: TMS320F28075

Tool/software:

Hi E2E.
I hope you can help to clarify a concern we just discovered. It has come to our attention that there is a max limitation of the 3.3V supply pins ramp rate of 10ms.
But we have this issue that we have a lot of capacitances for Brown-out events, so it is possible for us to save all the logs and go into a safe state before a UVLO kills the DSP. The pitfall is that the ramp-up time is very long. 3V3 soft-start-time is 250ms.
So what to do, it that an issue you think? - what is the electrical issue in having a very low dv/dt supply ramp (long ramp time)
The XRS pin is release by a Voltage Detector TLV840MADL30DBVR.
  • 0
    TI__Expert 7160 points

    Hello,

    I will take another look at it beginning next week and get back to you. If needed I will get more information from design team. Sorry for the delay.

  • 0
    TI__Expert 7160 points

    Hello,

    With initial look, the biggest problem with a slow ramp rate is the risk of toggling the reset when the voltage is around the POR and BOR thresholds. If the ramp is slow enough and the device pulls sufficient current, the voltage can bounce back and forth between these threshold values, inadvertently triggering POR or BOR resets.

     In general, it is not recommended to keep any pin near a mid-rail voltage for an extended period, as this causes extra wear/tear and accelerates IO aging.

    It cannot be guaranteed that every datasheet specification will be met during normal operation if the power ramping requirements are not met and recommended operating range is not followed. 

    I will keep you updated if design team has more feedback on this query.

  • 0 in reply to Stevan Duraskovic
    Prodigy 20 points

    Hi,

    Thanks for getting back to me with an initial look.


    I do not understand what the issue is with the POR and BOR reset when the IC is kept reset by the XRS pin. How is this an issue then?
    What do you mean with sufficient current? any values? where from? do I need to limit the current? to what?

    I am not keeping any pins near a mid-rail voltage, it is the rails I am writing about - all pins are eighter following the rail 100% or Grounded. Nothing in-between.

    If it have anything to do with high current usage from the supply, could I then get a number of what is a safe region of current consumption or energy during start-up?

  • 0 in reply to Soeren Juul
    TI__Expert 7160 points

    Hello Soeren,

    Since there is an external supervisor in place monitoring VDDIO rail, you won’t be impacted by the toggling effect that we note in the Data sheet. 

    Are you using the internal VREG on this device (VREGENZ pin tied to VSS)?  If you are using the internal VREG then there is no issue with the ramp rate. Hope this helps.

  • 0 in reply to Stevan Duraskovic
    Prodigy 20 points

    Perfect, thanks. VREGENZ is connected to VSS in my design, so all is great.