Part Number: TMS320F28388D
Tool/software:
Hi,
My system originally uses a 25 MHz external clock, and the PLL is configured to generate a 200 MHz PLLSYSCLK.
Now, when I cutoff the external clock, the DCC detects a clock failure, and then the system will switch the clock source to INTOSC1 and reconfigures the PLL so that PLLSYSCLK remains at 200 MHz.
However, when I call SysCtl_setClock() to update the clock settings, the function returns false. After checking the SysCtl_setClock(), I found that it times out while waiting for the PLL to lock, and the failure occurs during the SysCtl_isPLLValid() check.
The procedure for updating the clock settings after a clock failure is detected is as follows:
- Configure oscillator source to INTOSC1
- Delay of at least 60 OSCCLK cycles
- Turn off PLL
- Delay of at least 66 OSCCLK cycles required post powerdown of PLL
- reset MCD
- call the SysCtl_setClock(DEVICE_SETCLOCK_INTOSC)
define of the DEVICE_SETCLOCK_INTOSC:
#define DEVICE_SETCLOCK_INTOSC (SYSCTL_OSCSRC_OSC1 | SYSCTL_IMULT(80) | \ SYSCTL_REFDIV(2) | SYSCTL_ODIV(2) | \ SYSCTL_SYSDIV(1) | SYSCTL_PLL_ENABLE | SYSCTL_DCC_BASE_1 )
Is there any missing procedure that would lead the PLL lock timeout and the PLL valid failed?
Here is the code after the clock failure detected:
//
// Wait till the ISR is hit on clock failure
//
while(isr_enter != 0x1U);
//
// Configure oscillator source to INTOSC1
//
SysCtl_selectOscSource(SYSCTL_OSCSRC_OSC1);
//
// Delay of at least 60 OSCCLK cycles
//
SysCtl_delay(11U);
//
// Turn off PLL
//
EALLOW;
HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &=
~SYSCTL_SYSPLLCTL1_PLLEN;
EDIS;
//
// Delay of at least 66 OSCCLK cycles required post
// powerdown of PLL
//
SysCtl_delay(12U);
//
// Set up PLL control and clock dividers
//
SysCtl_resetMCD();
SysCtl_setClockTest(DEVICE_SETCLOCK_INTOSC);