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TMS320F280039: internal pull down resistance behavior difference in low temperature

Terry Deng
Expert 3015 points
Part Number: TMS320F280039
Other Parts Discussed in Thread: LM2901,

Tool/software:

customer report the internal pull down resistance value looks much difference in low temperature, they do the test as below, please help review if it make sense?

Below is their circuit, LM2901 output to F280039 IO (signal mark as 12VOVP_GLBLE) through diode DA125, with external cap (1nF) in the IO which enable internal pull down.

LM2901 output high at beginning so that CAP will be charged, then LM2901 output low so that CAP should discharge through IO internal pull down resistor.

1,    In 25c normal temperature,  read the IO status from high to low <1 second

2,    In -40c low temperature, read the IO status from high to low >15 second

3,    In -40c low temperature, add external 20K pull down resistor in the IO, read IO status from high to low <1 second

  • 0
    TI__Expert 5700 points

    Hello,

    The customer’s results make sense and align with how the device behaves at different temperatures.

    The input pin on the TMS320F280039 does not have a defined internal pull-down resistance value. The pull device is implemented with MOSFETs, and its effective resistance can vary widely (typically tens of kΩ) depending on process, supply, and temperature. You can calculate the resistance in normal temperature from Table in here:

    At low temperatures (−40 °C), the internal pull device’s on-resistance can increase significantly (due to reduced carrier mobility), resulting in a much weaker pull-down current. Consequently, the external 1 nF capacitor discharges very slowly, and the input voltage takes longer to fall below the input threshold, explaining the 15 s delay.

    When the external 20 kΩ pull-down resistor is added, the RC time constant is dominated by this resistor instead of the weak internal one, restoring a normal discharge rate (<1 s), as observed.

    For reliable discharge behavior over temperature, an external pull-down is recommended rather than relying on the internal pull. The internal pull-down is primarily for logic biasing under static conditions, not for discharging capacitive nodes. Alternatively, the capacitor value can be reduced if the external pull-down cannot be used.

    Best Regards,

    Masoud