Other Parts Discussed in Thread: LAUNCHXL-F280025C, C2000WARE
Hi,
I have configure the EPWM1 module of the F280025C to trigger a TZ interrupt from the DCAEVT1.inter signal, which is trigerred by the CMPSS3H filtered signal. The configuration of the EPWM1 module is shown at the end.
Once the CMPSS3H signal goes high (which is being monitored through a GPIO), the ISR for the EPWM1_TZ is executed, as expected. The interrupt is not acknowled inside the ISR.
Inside another function, which runs at a fixed time base, the following code is executed:
EALLOW;
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 0; // Event disabled
EPwm1Regs.TZEINT.bit.DCAEVT1 = 0;
EDIS;
//
// Clear CMPSS flag
//
EALLOW;
EPwm1Regs.TZCLR.bit.DCAEVT1 = 1; // Clear event latch
EPwm1Regs.TZCLR.bit.INT = 1; // Clear TZ INT flag
EDIS;
// Acknowledge the interrupt
PieCtrlRegs.PIEACK.all = PIEACK_GROUP2;It was expected to disable the mechanisms to trigger the EPWM1_TZ interrupt by the DCAEVT1. Nonetheless, as soon as the EPWM1_TZ interrupt is acknowledged, it's retriggered. Even though the CMPSS3H filtered signal is low (monitored through a GPIO), the DCAEVT1 is disabled and the DCAEVT1 interrupt is disabled. I would like to know why is the EPWM1_TZ interrupt being retriggered?
EPWM1 module configuration:
// Disable the ePWM1 module before configuration
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0;
// Configure the Time-Base (TB) Submodule
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Up-count mode
EPwm1Regs.TBPRD = PWM_TIME_BASE_PERIOD; // Set the period value
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase is 0
EPwm1Regs.TBCTR = 0; // Clear counter
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Clock pre-scale
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock high speed pre-scale
// Configure the Counter-Compare (CC) Submodule
EPwm1Regs.CMPA.bit.CMPA = 1;//PWM_TIME_BASE_PERIOD / 2; // Set compare A value (50% duty cycle)
// Configure the Action-Qualifier (AQ) Submodule
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear output A on up-count
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set output A on zero
// Configure the Event-Trigger (ET) Submodule
EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_ZERO; // Select SOC on counter zero
EPwm1Regs.ETPS.bit.SOCAPRD = ET_1ST; // Generate pulse on 1st event
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
//
// Bypass CMPSS output signal through ePWM-XBAR
//
/* 1) Select MUX4.0 (CMPSS3H) for TRIP4 */
EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX4 = 0; /* MUX4.0 → CMPSS3H */
/* 2) Enable that MUX path */
EPwmXbarRegs.TRIP4MUXENABLE.all = 0x0000;
EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX4 = 1; /* gate it on */
//
// Bypass CMPSS output signal through Digital Compare submodule
//
// Select which signal goes to DCAH (TRIP4 → DCAH)
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 4-1;
// Select which signal goes to DCAEVT1 (DCAH → DCAEVT1)
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; // DCAEVTI Selection: DCAH = high, DCAL = don't care
// Select version of DCAEVT1 (not filtered, synchronous)
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; /* Event source = DCAEVT1 */
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; /* Synchronous */
//
// Configure Trip Zone submodule to generate interrupt from CMPSS output signal
//
/* 2) Define what happens to the PWM pins when that event occurs
-> “do nothing” */
EPwm1Regs.TZCTL.bit.TZA = TZ_NO_CHANGE; /* 11b = no change */
EPwm1Regs.TZCTL.bit.TZB = TZ_NO_CHANGE;
/* 3) Enable the DCAEVT1 interrupt inside the module */
EPwm1Regs.TZEINT.all = 0; /* clear all enables */
EPwm1Regs.TZEINT.bit.DCAEVT1 = 1; /* enable local INT */
// Enable the ePWM1 module
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
Device / Tools
- Device: LAUNCHXL-F280025C
- CCS: 12.7.1.00001
- Compiler: TI v22.6.1 LTS
- C2000Ware: C2000Ware_5_02_00_00