TMS320F28P650DK: EtherCAT clock errors at high temperatures

Any update here?

Hi Leo,

We are looking into this and will get back to you as soon as possible. Thank you.

Best Regards,

Aishwarya

Hello,

Leo Wu said:

The clock of PHY will be 50MHz (abnormal), when the chip is at high temperature.

Does ETHERCATPHYCLK only exhibit abnormal behavior when the chip is at high temperatures? Is performance normal at room temp?

Best,

Matt

Hello,

Can you also confirm the delay value currently set for SYSCTL_REGWRITE_DELAY in SysCtl_setECatClk()? Please try increasing to 300 NOP delay and confirm if the issue is still observed.

Best,

Matt 

Hi Matt，

I will let the customer try this solution.

This issue can be reproduced by using hot air gun to blow the chip. The customer use this method to simulate the working conditions of the faulty chip. When the chip works at the room temp, the clock is normal. The customer report that they find 1 faulty chip in 300 products. By the way, are there any difference between AUXPLL and SYSPLL?

Thanks,

Leo

Hello Leo,

Leo Wu said:

I will let the customer try this solution.

Please keep us updated on the outcome.

Leo Wu said:

By the way, are there any difference between AUXPLL and SYSPLL?

I will have to check on this internally, I anticipate it will take a few days to get information prepared.

Best,

Matt

Hi Matt,

My customer has added the delay as follow:

The situation has improved, however the issue still occur.

Before add the code, they will meet the issue every time they boot the MCU at the high temperature.

After add the code, the issue will occur about once every 15 times.

Thanks,

Leo

Hello Leo,

Leo Wu said:

By the way, are there any difference between AUXPLL and SYSPLL?

To follow up: there are no differences between AUXPLL and SYSPLL.

Leo Wu said:

After add the code, the issue will occur about once every 15 times.

Can you change the delay code to the following? The RPT op-code only allows for a 8-bit count specifier. 

asm(" RPT #250 || NOP \n RPT #50 || NOP")

Best,

Matt

Hi Matt,

It's a pity that customer feedback here is no improvement after using asm(" RPT #250 || NOP \n RPT #50 || NOP").

Here is the error clock.

Thanks,

Leo

Hello Leo,

Apologies, I missed this in the initial look over their code, but please ensure the customer adds the 300 cycle delay after both writes to ETHERCATCLKCTL:

Best,

Matt

Hi Matt,

The customer is testing this solution. The customer want to know the principle of this solution.

Thanks,

Leo