TMS320F28377D: Break error when data is sent before SCI initialization

Hello,

I'd recommend to review the explanation of the break detect feature in the SCI chapter of the device TRM. Please double check your init sequence. To  me it sounds like you are enabling the SCI before the other device has started sending data. In this case, the RX line is probably low, which causes the break error. You can try to add a pull-up resistor to RX to see the break error goes away. The pull up will ensure the RX line is high by the time the MCU is out of reset. 

Thank you for your response.
However, the sequence I’m referring to is different from what you described.
The issue I’m facing is caused by the following sequence:
SCI is sent → my device starts initializing.
I appreciate your help and look forward to your thoughts.

The SCI RX pin is driven by your "other" device. This pin needs to be HIGH before the SCI on the MCU is enabled to avoid the BREAK condition.

Thank you again for your continued support.
I’d like to clarify the sequence and share an additional observation that may help narrow down the issue.
In my setup, the external device continuously transmits data, and this transmission begins before the SCI module on the F28377D is initialized.
I’ve confirmed that when the external device does not transmit, no BREAK error occurs — even if the SCI is initialized later.
This suggests that the BREAK condition is not simply due to the RX line being LOW by default, but rather due to active transmission occurring while the SCI is not yet ready.
Since the external device cannot delay its transmission, I’m looking for a way to handle this timing mismatch on the MCU side.
Do you have any recommendations for safely initializing the SCI under these conditions, or for ignoring incoming data until the module is fully ready?

Thanks for the added details. Please check the SCI init software sequence on the C2000 side. One possibility is that the SCI is initialized & enabled before the pinmux of the C2000 is set. This will block the external RX pin from the SCI until the pinmux is setup, possibly leading to the break error. You can import any of the SCI examples in C2000ware to review the init sequence. 

There is also an internal pull-up option on all GPIO pins of the MCU. You can try to enable this internal pull-up on the RX GPIO and see if there is any difference in behavior. 

Thank you again for your continued support.
I checked the SCI registers after enabling the internal pull-up resistor.
However, the TMS320F28377D still occasionally detects a break condition in this setup.
I also measured the voltage near the SCIRX pin, but I did not observe any prolonged low-level voltage.
Thank you.

I'm still not clear on your pin mux and SCI init sequence. Can you clarify? 

Also, what clock mode are you using for the MCU? INTOSC, external crystal? 

Hello,
I apologize for the delayed response and for any confusion caused. I was previously posting under a different account, but due to login issues, I want to continue the discussion using another account.
Thank you for your continued support. I’d like to share the SCIC initialization sequence and corresponding source code.

Clock Configuration
• External Crystal Oscillator: 16 MHz
• System Clock: 156 MHz
Initialization Sequence
1. GPIO Configuration (Core 1)
2. Core 2 Flash Boot
3. GPIO Configuration (Core 2)
4. SCI Configuration (Core 2)

Code
/* Clock Configuration */
/* • External Crystal Oscillator: 16 MHz */
/* • System Clock : 156 MHz */
#define VAL_PCLKCR7 0x00000006
#define INIT_SCIC_SCICTL1 0x0003
#define VAL_SCIC_SCICCR 0x0027
#define VAL_SCIC_SCIHBAUD 0x0000
#define VAL_SCIC_SCILBAUD 0x00A8
#define VAL_SCIC_SCICTL2 0x0000
#define INIT_SCIC_SCIFFTX 0x4060
#define INIT_SCIC_SCIFFRX 0x4061
#define VAL_SCIC_SCIFFCT 0x0000
#define VAL_SCIC_SCIPRI 0x0000
#define VAL_SCIC_SCIFFTX 0xE060
#define VAL_SCIC_SCIFFRX 0x6061
#define VAL_SCIC_SCICTL1 0x0023

void vInitSciPeri( void );
void vReadyInitSciPeri( void );
void vSetSciCRegs( void );
/**********************************************************************************************************************
**********************************************************************************************************************/
void vInitSciPeri( void ) {
vReadyInitSciPeri();
vSetSciCRegs();
}

/**********************************************************************************************************************
**********************************************************************************************************************/
void vReadyInitSciPeri( void ) {
__eallow();
g_stRegsCpuSys.uPCLKCR7.dwWord = ( unsigned long )VAL_PCLKCR7;
__edis();
}

/**********************************************************************************************************************
**********************************************************************************************************************/
void vSetSciCRegs( void ) {
__eallow();

/* SCIC Control Register 1: Enable transmission and reception; reset enabled; error interrupts disabled */
g_stRegsSciC.uSCICTL1.unWord = ( unsigned int )INIT_SCIC_SCICTL1;

/* SCIC Communications Control Register:
o 1 word = 8 bits
o No address bit addition
o Loopback mode disabled
o Parity bit enabled
o 1 stop bit
*/
g_stRegsSciC.uSCICCR.unWord = ( unsigned int )VAL_SCIC_SCICCR;

/* SCIC Control Register 1 (Updated): Enable reception and transmission; error interrupts disabled */
g_stRegsSciC.uSCICTL1.unWord = ( unsigned int )VAL_SCIC_SCICTL1;

/* SCIC Baud Rate High Register: Set BRR = 168 */
g_stRegsSciC.uSCIHBAUD.unWord = ( unsigned int )VAL_SCIC_SCIHBAUD;

/* SCIC Baud Rate Low Register: Set BRR = 168 */
g_stRegsSciC.uSCILBAUD.unWord = ( unsigned int )VAL_SCIC_SCILBAUD;

/* SCIC Control Register 2: Enable TXRDY, RXRDY, and BRKDT interrupts */
g_stRegsSciC.uSCICTL2.unWord = ( unsigned int )VAL_SCIC_SCICTL2;

/* SCIC FIFO Transmit Register: Disable transmit FIFO interrupt; reset transmit FIFO */
g_stRegsSciC.uSCIFFTX.unWord = ( unsigned int )INIT_SCIC_SCIFFTX;

/* SCIC FIFO Receive Register: Enable receive FIFO interrupt on 1 byte; reset receive FIFO */
g_stRegsSciC.uSCIFFRX.unWord = ( unsigned int )INIT_SCIC_SCIFFRX;

/* SCIC FIFO Control Register: No delay */
g_stRegsSciC.uSCIFFCT.unWord = ( unsigned int )VAL_SCIC_SCIFFCT;

/* SCIC SCI Priority Control: Immediately stop transmission when breakdown occurs */
g_stRegsSciC.uSCIPRI.unWord = ( unsigned int )VAL_SCIC_SCIPRI;

/* SCIC FIFO Transmit Register (Updated): Disable transmit FIFO interrupt; release transmit FIFO reset */
g_stRegsSciC.uSCIFFTX.unWord = ( unsigned int )VAL_SCIC_SCIFFTX;

/* SCIC FIFO Receive Register (Updated): Enable receive FIFO interrupt on 1 byte; release receive FIFO reset */
g_stRegsSciC.uSCIFFRX.unWord = ( unsigned int )VAL_SCIC_SCIFFRX;

/* SCIC Control Register 1 (Final): Enable transmission and reception; release reset; error interrupts disabled */
g_stRegsSciC.uSCICTL1.unWord = ( unsigned int )VAL_SCIC_SCICTL1;

__edis();
}

Hi,

?? ?? said:

Clock Configuration
• External Crystal Oscillator: 16 MHz
• System Clock: 156 MHz
Initialization Sequence
1. GPIO Configuration (Core 1)
2. Core 2 Flash Boot
3. GPIO Configuration (Core 2)
4. SCI Configuration (Core 2)

Thanks for providing the init sequence. This looks ok. 

?? ?? said:

void vSetSciCRegs( void ) {

I would suggest taking a look at the SCI configuration steps in the SCI bit field examples in C2000ware to understand if there may be a difference in your SCI configuration which could explain the break issue you are facing.

C:\ti\c2000\C2000Ware_6_00_00_00\device_support\f2837xd\examples\cpu1\sci_loopback

C:\ti\c2000\C2000Ware_6_00_00_00\device_support\f2837xd\examples\cpu1\sci_echoback