Part Number: TMS320F28027
Hi Experts,
My cusomter using DB with a small duty in the PWM. They are seeing the below behaviour:
Green: EPWMA
Blue: EPWMB
- The duty cycle is small, with the DB delays in blue FED and greed RED, you may see the blue have a very short high-time, this is expected
- Now, they further reduce the duty of the raw input that the DBFED and DBRED is equal / larger than the duty. They expect the high-time of the blue would futher reduce and may reduce to none, however what they see is like below
Could you pleaes help explaining this behaviour?
We are guessing that it's the DB delay that changes the order of the edges. For example, the blue should first have a rising edge then a falling edge, however, the rising edge is delayed by DB so that the falling edge would come fisrt. Iit's this possible?
I am also attaching the PWM configuration here:
EALLOW;
EPwm4Regs.TZCTL.bit.TZA = 0x02; //Force EPWMxA to a high state
EPwm4Regs.TZCTL.bit.TZB = 0x02; //Force EPWMxB to a high state
EPwm4Regs.TZFRC.bit.OST = 0x01; // Forces a one-shot trip event and sets the OSTFLG bit
EDIS;
EPwm4Regs.TBPRD = 750;
EPwm4Regs.TBPHS.half.TBPHS = 0;
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = 0x02; //Up-Down mode
EPwm4Regs.TBCTL.bit.PHSEN = 0x01; //Sync ensable
EPwm4Regs.TBCTL.bit.PRDLD = 0x00; //Shadow mode
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0x00; //Synchronized while TBCNT=0
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0x00; //TBCLK = SYSCLK / (HSPCLKDIV * CLKDIV) = 100MHz/(1*1)=100MHz
EPwm4Regs.TBCTL.bit.CLKDIV =0x00;
EPwm4Regs.TBCTL.bit.PHSDIR = 0x00;
EPwm4Regs.CMPA.half.CMPA = 1;
EPwm4Regs.CMPB = 1;
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0x00; //Shadow mode
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0x00; //Shadow mode
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0x02; //Load on CTR = Zero or PRD
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0x02; //Load on CTR = Zero or PRD
EPwm4Regs.AQCTLA.bit.CAU = 0x02; //AQ_CLEAR; //CNT = CMPA up ->0
EPwm4Regs.AQCTLA.bit.CAD = 0x01; //AQ_SET; //CNT = CMPB down ->1
EPwm4Regs.AQCTLA.bit.CBU = 0x00;
EPwm4Regs.AQCTLA.bit.CBD = 0x00;
EPwm4Regs.AQCTLA.bit.PRD = 0x00;
EPwm4Regs.AQCTLA.bit.ZRO = 0x00;
EPwm4Regs.AQCTLB.bit.CAU = 0x02; //AQ_CLEAR; //CNT = CMPA up ->0
EPwm4Regs.AQCTLB.bit.CAD = 0x01; //AQ_SET; //CNT = CMPA down ->1
EPwm4Regs.AQCTLB.bit.CBU = 0x00;
EPwm4Regs.AQCTLB.bit.CBD = 0x00;
EPwm4Regs.AQCTLB.bit.PRD = 0x00;
EPwm4Regs.AQCTLB.bit.ZRO = 0x00;
EPwm4Regs.AQSFRC.bit.RLDCSF = 3; //The active register load immediately
EPwm4Regs.AQCSFRC.bit.CSFA = 0x01; //FORCE LOW
EPwm4Regs.AQCSFRC.bit.CSFB = 0x02; //FORCE the EPWM3B output LOW
EPwm4Regs.DBCTL.bit.IN_MODE =0x02; //EPWMxA In is the source for rising-edge delayed signal.
//EPWMxB In is the source for falling-edge delayed signal.
EPwm4Regs.DBCTL.bit.POLSEL = 0x02; //Active high complementary (AHC). EPWMxB is inverted.
EPwm4Regs.DBCTL.bit.OUT_MODE = 0x03; //Enable dead band time configuration
EPwm4Regs.DBRED = 60; //SYSCLK/EPWM2_DB = 60M/0.7M
EPwm4Regs.DBFED = 60; //SYSCLK/EPWM2_DB = 60M/0.7M
EPwm4Regs.PCCTL.bit.CHPEN = 0x00; //Disable chopping function
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
